Exam timer

Claim 2

A timing device for pacing an examinee through an examination having a number of questions and a time interval in which to answer the questions, said timing device comprising: A) clock means for generating a real time signal indicative of the present time; B) operator controlled input means for entering a plurality of signals corresponding to the number of questions and the time interval; C) memory means for storing said plurality of signals; D) control means connected to said clock means, said memory means, and said input means, said control means being operative to : i) determine a response time in which to answer each of the questions by dividing the time interval by the number of questions; ii) successively decrement the time interval by the response time until the time interval equals zero; iii) successively increment the number of questions by one each time the time interval is decremented; iv) successively generate time signals corresponding to the successively decremented time intervals; and v) successively generate number signals corresponding to the successively incremented number of questions; and E) display means in communication with said control means for displaying the time and number signals successively generated by the control means such that the examinee may determine from the display means the time interval remaining until the examination is over and the question number he/she should be answering in order to complete the examination on time.

Claim 3

The timing device of claim 1 wherein the operator controlled input means further includes means for entering a plurality of signals corresponding to the current time, the control means is further operative to continuously update the inputted current time signals, and the display means further includes means for displaying the continuously updated current time signals.

Claim 4

The device of claim 1 wherein the display means further comprises LCD means for continuously displaying a digital read-out of the continuously generated time and number signals.

Claim 5

The device of claim 1 wherein the clock means, the memory means, the control means and the display means further comprise an integrated circuit.

Claim 6

The device of claim 4 further comprising a housing for containing and protectively encasing said integrated circuit.

Claim 7

The device of claim 5 wherein the housing further comprises a window through which said display means may be observed.

Claim 8

The device of claim 1 wherein the input means further comprises a plurality of switches.

Claim 9

The device of claim 1 further comprising switch means in communication with the control means wherein the control means begins successively decrementing the time interval and incrementing the number of questions upon activation of the switch.

Claim 10

The device of claim 8 further comprising a mode switch for switching the device between a setting mode, to permit entry of said plurality of signals, and a running mode, to permit entry of a start signal from activation of the start switch.

Claim 11

A timing device for pacing an examinee through an examination having a number of questions and a time interval in which to answer the questions, said timing device comprising: A) clock means for generating a real time signal indicative of the present time; B) operator controlled input means for entering a plurality of signals corresponding to the current time, the number of questions and the time interval; C) memory means for storing said plurality of signals; D) control means connected to said clock means, said memory means, and said input means, said control means being operative to: i) continuously update the current time signal; ii) determine a response time in which to answer each of the questions by dividing the time interval by the number of questions; iii) successively decrement the time interval by the response time until the time interval equals zero; iv) successively incremented the number of questions by one each time the time interval is decremented; v) successively generate time signals corresponding to the successively decremented time intervals; and vi) successively generate number signals corresponding to the successively incremented number of questions; E) switch means in communication with the control means, activation of which causes the control means to begin successively decrementing the time interval and incrementing the number of questions; F) display means in communication with said control means for displaying the continuously updated current time signal, and the time and number signals successively generated by the control means such that the examinee may determine from the display means the current time, the time interval remaining until the examination is over and the question number he/she should be answering in order to complete the examination on time.

Claim 12

A timing device for pacing an examinee through an examination having a number of questions and a time interval in which to answer the questions, said timing device comprising: A) clock means for generating a real time signal indicative of the present time; B) operator controlled input means for entering a plurality of signals corresponding to the current time, the number of questions and the time interval; C) memory means for storing said plurality of signals; D) control means connected to said clock means, said memory means, and said input means, said control means being operative to: i) continuously update the current time signal; ii) determine a response time in which to answer each of the questions by dividing the time interval by the number of questions; iii) successively decrement the time interval by the response time until the time interval equals zero; iv) successively incremented the number of questions by one each time the time interval is decremented; v) successively generate time signals corresponding to the successively decremented time intervals; and vi) successively generate number signals corresponding to the successively incremented number of questions; E) switch means in communication with the control means, activation of which causes the control means to begin successively decrementing the time interval and incrementing the number of questions; F) display means in communication with said control means for displaying the continuously updated current time signal, and the time and number signals successively generated by the control means such that the examinee may determine from the display means the current time, the time interval remaining until the examination is over and the question number he/she should be answering in order to complete the examination on time.

Claim 13

The device of claim 10 wherein the display means further comprises LCD means for continuously displaying a digital read-out of the continuously generated time and number signals.

Claim 14

The device of claim 10 wherein the clock means, the memory means, the control means and the display means further comprise an integrated circuit.

Claim 15

The device of claim 12 further comprising a housing for containing and protectively encasing said integrated circuit.

Claim 16

The device of claim 13 wherein the housing further comprises a window through which said display means may be observed.

Claim 17

The device of claim 10 wherein the input means further comprises a plurality of switches.

Claim 18

The device of claim 10 further comprising a mode switch for switching the device between a setting mode, the permit entry of said plurality of signals, and a running mode, to permit entry of a start signal from activation of the start switch.

Claim 19

A timing device for pacing an examinee through an examination having a number of questions and a time interval in which to answer the questions, said timing device comprising: A) clock means for generating a real time signal indicative of the present time; B) operator controlled input means for entering a plurality of signals corresponding to the current time, the number of questions and the time interval; C) memory means for storing said plurality of signals; D) control means connected to said clock means, said memory means, and said input means, said control means being operative to: i) continuously update the current time signal; ii) determine a response time in which to answer each of the questions by dividing the time interval by the number of questions; iii) successively decrement the time interval by the response time until the time interval equals zero; iv) successively increment the number of questions by one each time the time interval is decremented; v) successively generate time signals corresponding to the successively decremented time intervals; and vi) successively generate number signals corresponding to the successively incremented number of questions; E) switch means in communication with the control means, activation of which causes the control means to begin successively decrementing the time interval and incrementing the number of questions; F) a mode switch for switching the device between a setting mode, to permit entry of said plurality of signals, and a running mode, to permit entry of a start signal from activation of the start switch; and G) display means in communication with said control means for displaying the continuously updated current time signal, and the time and number signals successively generated by the control means such that the examinee may determine from the display the current time, means the time interval remaining until the examination is over and the question number he/she should be answering in order to complete the examination on time.

Claim 20

A timing device for pacing an examinee through an examination having a number of questions and a time interval in which to answer the questions, said timing device comprising: A) clock means for generating a real time signal indicative of the present time; B) operator controlled input means for entering a plurality of signals corresponding to the current time, the number of questions and the time interval; C) memory means for storing said plurality of signals; D) control means connected to said clock means, said memory means, and said input means, said control means being operative to: i) continuously update the current time signal; ii) determine a response time in which to answer each of the questions by dividing the time interval by the number of questions; iii) successively decrement the time interval by the response time until the time interval equals zero; iv) successively increment the number of questions by one each time the time interval is decremented; v) successively generate time signals corresponding to the successively decremented time intervals; and vi) successively generate number signals corresponding to the successively incremented number of questions; E) switch means in communication with the control means, activation of which causes the control means to begin successively decrementing the time interval and incrementing the number of questions; F) a mode switch for switching the device between a setting mode, to permit entry of said plurality of signals, and a running mode, to permit entry of a start signal from activation of the start switch; and G) display means in communication with said control means for displaying the continuously updated current time signal, and the time and number signals successively generated by the control means such that the examinee may determine from the display the current time, means the time interval remaining until the examination is over and the question number he/she should be answering in order to complete the examination on time.

Claim 21

The device of claim 10 wherein the display means further comprises LCD means for continuously displaying a digital read-out of the continuously generated time and number signals.

Claim 22

The device of claim 17 wherein the clock means, the memory means, the control means and the display means further comprise an integrated circuit.

Claim 23

The device of claim 19 further comprising a housing for containing a protectively encasing said integrated circuit.