Sense amplifier driver for memory device having reduced power dissipation

Claim 1

A sense amplifier driver including a sensing clock driver for delivering a sensing enable signal in response to a sensing clock signal, said sensing enable signal being delivered to a sensing enable terminal of a data sensing amplifier coupled between a pair of bit lines, and a restoring clock driver for delivering a restoring enable signal to a restoring enable terminal of said data sensing amplifier in response to a restoring clock signal, a rising edge and a falling edge of said sensing enable signal having multi-slope characteristics, said sensing clock driver further comprising: a first inverter for respectively generating a first output signal and a second output signal in response to said sensing clock signal, said first output signal having a rapid rising transient edge and a slow falling transient edge, said second output signal having a slow rising transient edge and a rapid falling transient edge: a second inverter, having a p-channel MOS transistor and an n-channel MOS transistor, for inverting said second output signal of the first inverter; a p-channel MOS transistor having a gate coupled with said first output signal of the first inverter, a drain coupled to an output terminal of said second inverter and a source coupled with a power source voltage, and having a current driving capability larger than that of said p-channel MOS transistor of the second inverter, said p-channel MOS transistor being slowly turned on and rapidly turned off in response to said first output signal of the first inverter; and an n-channel MOS transistor having a gate coupled to said output terminal of the second inverter, a source coupled to said sensing enable terminal of the data sensing amplifier and a drain coupled with a ground voltage.