Patent US5140193A successfully refreshed from Google Patents.
US5140193A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable connector for programmable logic device
Assignee: Xilinx Inc
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Filing: 1990-03-27
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Granted: 1992-08-18
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Expires: 2010-03-27
Abstract
Abstract A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins. An application of the decoder circuit is described for use with a latch as a data/address demultiplexer.
Inventors
- 👤 Ross H. Freeman, deceased
- 👤 Khue Duong
- 👤 Hung-Cheng Hsieh
- 👤 Charles R. Erickson
- 👤 William S. Carter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
208 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; at least one programmable interconnect corresponding to one of said at least one I/O line and one of said at least one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line; programmable control means for controlling said means for applying a first voltage, said programmable control means being programmable to at least a first state such that in said first state said means for applying a first voltage provides said first voltage to said corresponding interconnect line in response to a first signal on said corresponding I/O line and provides a high impedance to said corresponding interconnect line in response to a second signal on said corresponding I/O line; means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage; and means for programmably applying one of a signal present on said interconnect line and the complement of said signal present on said interconnect line to one of said at least one I/O line.
Claim 2
Dependent Claim
208 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; at least one programmable interconnect corresponding to one of said at least one I/O line and one of said at least one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line; programmable control means for controlling said means for applying a first voltage, said programmable control means being programmable to at least a first state such that in said first state said means for applying a first voltage provides said first voltage to said corresponding interconnect line in response to a first signal on said corresponding I/O line and provides a high impedance to said corresponding interconnect line in response to a second signal on said corresponding I/O line; means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage; and means for programmably applying one of a signal present on said interconnect line and the complement of said signal present on said interconnect line to one of said at least one I/O line.
Claim 3
Dependent Claim
32 words
A programmable connector as in claim 1 in which said at least one I/O line is a plurality of I/O lines, and one programmable interconnect corresponds to each of said I/O lines.
Claim 4
Dependent Claim
32 words
A programmable connector as in claim 1 in which said at least one interconnect line is a plurality of interconnect lines and one programmable interconnect corresponds to each of said interconnect lines.
Claim 5
Dependent Claim
59 words
A programmable connector as in claim 1 in which said at least one I/O line is a plurality of I/O lines, said at least one interconnect line is a plurality of interconnect lines, and at least one programmable interconnect corresponds to each of said I/O lines and at least one programmable interconnect corresponds to each of said interconnect lines.
Claim 6
Dependent Claim
80 words
A programmable connector as in claim 1, in which said at least one I/O line is a plurality of I/O lines, said programmable connector further comprising: means for programmably applying a signal present on one of said at least one interconnect line to one of said plurality of I/O lines, and means for programmably applying the complement of said signal present on said one of said at least one interconnect line to said one of said plurality of I/O lines.
Claim 7
Dependent Claim
24 words
A programmable connector as in claim 1 further comprising an external pin connected to at least one of said at least one I/O line.
Claim 8
Dependent Claim
33 words
A programmable connector as in claim 1 further comprising means for placing at least one signal generated internally to an integrated circuit onto at least one of said at least one I/O line.
Claim 9
Dependent Claim
75 words
A programmable connector as in claim 1 in which said programmable control means is further programmable to at least a second state such that in said second state said means for applying a first voltage provides said first voltage to said corresponding interconnect line in response to said second signal on said I/O line and provides a high impedance to said corresponding interconnect line in response to said first signal on said corresponding I/O line.
Claim 10
Dependent Claim
51 words
A programmable connector as in claim 1 in which said programmable control means is further programmable to a state in which said means for applying a first voltage provides a high impedance to said corresponding interconnect line in response to both said first and second signals on said corresponding I/O line.
Claim 11
Dependent Claim
31 words
A programmable connector as in claim 1 or 8 in which said means for programmably applying can be programmed to apply a high impedance to said at least one I/O line.
Claim 12
Dependent Claim
47 words
A programmable connector as in claim 1 or 8 in which said at least one I/O line, said at least one interconnect line, and said at least one programmable interconnect are located between the edge of an integrated circuit and logic circuitry internal to said integrated circuit.
Claim 13
Dependent Claim
117 words
A programmable connector as in claim 1 or 8 further comprising a latch inserted between said I/O line and said programmable interconnect, said latch comprising a data port connected to said I/O line, an enable port, and an output port connected to said programmable interconnect, said output port being connected to said I/O line when a signal on said enable port has a first state and said output port being disconnected from said I/O line when a signal on said enable port has a second state, said output port providing to said programmable interconnect a signal related to a signal present on said I/O line when said signal on said enable port has had said first state.
Claim 14
Dependent Claim
150 words
A programmable connector for a programmable logic device comprising: a plurality of input lines; at least one interconnect line; at least one programmable interconnect, each corresponding to one interconnect line and corresponding to a plurality of said independent input signals, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line; and programmable control means for controlling said means for applying a first voltage, said programmable control means being controlled by a programmable set of said independent input signals such that said means for applying said first voltage can be caused to apply said first voltage in response to a selected combination of said independent input signals; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 15
Dependent Claim
150 words
A programmable connector for a programmable logic device comprising: a plurality of input lines; at least one interconnect line; at least one programmable interconnect, each corresponding to one interconnect line and corresponding to a plurality of said independent input signals, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line; and programmable control means for controlling said means for applying a first voltage, said programmable control means being controlled by a programmable set of said independent input signals such that said means for applying said first voltage can be caused to apply said first voltage in response to a selected combination of said independent input signals; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 16
Dependent Claim
44 words
A programmable connector as in claim 13 in which said plurality of input lines, said at least one interconnect line, and said at least one programmable interconnect are located between the edge of an integrated circuit and logic circuitry internal to said integrated circuit.
Claim 17
Dependent Claim
32 words
A programmable connector as in claim 13 further comprising means for placing at least one signal generated internally to an integrated circuit onto at least one of said plurality of input lines.
Claim 18
Dependent Claim
136 words
A programmable connector as in claim 13 further comprising a latch inserted between at least one of said plurality of input lines and said programmable interconnect, said latch comprising a data port connected to said I/O line, an enable port, and an output port connected to said programmable interconnect, said output port being connected to said one of said plurality of input lines when a signal on said enable port has a first state and said output port being disconnected from said one of said plurality of input lines when a signal on said enable port has a second state, said output port providing to said programmable interconnect a signal related to a signal present on said one of said plurality of input lines when said signal on said enable port last had said first state.
Claim 19
Dependent Claim
24 words
A programmable connector as in claim 13 or 14 comprising an external pin connected to at least one of said plurality of input lines.
Claim 20
Dependent Claim
40 words
A programmable connector as in claim 1, 8 or 13 further comprising means for segmenting at least one of said at least one interconnect line comprising at least one controllable switching means located along said at least one interconnect line.
Claim 21
Dependent Claim
44 words
A programmable connector as in claim 1 or 13, in which said means for applying is a transistor having one current carrying terminal connected to said first voltage supply, another to said interconnect line and its control terminal connected to said programmable control means.
Claim 22
Dependent Claim
148 words
A programmable connector as in claim 19 in which said transistor is an N-channel FET and said programmable control means comprises: a NAND gate having an output terminal connected to said control terminal of said transistor, and at least two input terminals, each receiving input from an output terminal of a programmable logic gate, one said programmable logic gate having an input terminal connected to said I/O line and another input terminal connected to a memory cell which determines whether said logic gate will pass a signal from said I/O line to said NAND gate, and another said programmable logic gate having an input terminal connected to receive the complement of a signal on said I/O line and another input terminal connected to a memory cell which determines whether said another logic gate will pass said complement of said signal from said I/O line to said NAND gate.
Claim 23
Dependent Claim
204 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; means for segmenting at least one of said at least one interconnect line comprising at least one controllable switching means located along said at least one interconnect line; at least one programmable interconnect corresponding to one of said at least one I/O line and one of said at least one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line, and programmable control means for controlling said means for applying a first voltage, said programmable control means being programmable to at least a first state such that in said first state said mean for applying a first voltage provides said first voltage to said corresponding interconnect line in response to a first signal on said corresponding I/O line and provides a high impedance to said corresponding interconnect line in response to a second signal on said corresponding I/O line; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 24
Dependent Claim
204 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; means for segmenting at least one of said at least one interconnect line comprising at least one controllable switching means located along said at least one interconnect line; at least one programmable interconnect corresponding to one of said at least one I/O line and one of said at least one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line, and programmable control means for controlling said means for applying a first voltage, said programmable control means being programmable to at least a first state such that in said first state said mean for applying a first voltage provides said first voltage to said corresponding interconnect line in response to a first signal on said corresponding I/O line and provides a high impedance to said corresponding interconnect line in response to a second signal on said corresponding I/O line; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 25
Dependent Claim
283 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; at least one programmable interconnect corresponding to one of said at least one I/O line and one of said at least one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line, and programmable control means for controlling said means for applying a first voltage, said programmable control means being programmable to at least a first state such that in said first state said means for applying a first voltage provides said first voltage to said corresponding interconnect line in response to a first signal on said corresponding I/O line and provides a high impedance to said corresponding interconnect line in response to a second signal on said corresponding I/O line; and a latch inserted between said I/O line and said programmable interconnect, said latch comprising a data port connected to said I/o line, an enable port, and an output port connected to said programmable interconnect, said output port being connected to said I/O line when a signal on said enable port has a first state and said output port being disconnected from said I/O line when a signal on said enable port has a second state, said output port providing to said programmable interconnect a signal related to a signal present on said I/O line when said signal on said enable port last had said first state; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 26
Dependent Claim
283 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; at least one programmable interconnect corresponding to one of said at least one I/O line and one of said at least one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line, and programmable control means for controlling said means for applying a first voltage, said programmable control means being programmable to at least a first state such that in said first state said means for applying a first voltage provides said first voltage to said corresponding interconnect line in response to a first signal on said corresponding I/O line and provides a high impedance to said corresponding interconnect line in response to a second signal on said corresponding I/O line; and a latch inserted between said I/O line and said programmable interconnect, said latch comprising a data port connected to said I/o line, an enable port, and an output port connected to said programmable interconnect, said output port being connected to said I/O line when a signal on said enable port has a first state and said output port being disconnected from said I/O line when a signal on said enable port has a second state, said output port providing to said programmable interconnect a signal related to a signal present on said I/O line when said signal on said enable port last had said first state; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 27
Dependent Claim
77 words
A programmable connector as in claim 21 or 22 in which said programmable control means is further programmable to at least a second state such that in said second state said means for applying a first voltage provides said first voltage to said corresponding interconnect line in response to said second signal on said I/O line and provides a high impedance to said corresponding interconnect line in response to said first signal on said corresponding I/O line.
Claim 28
Dependent Claim
53 words
A programmable connector as in claim 21 or 22 in which said programmable control means is further programmable to a state in which said means for applying a first voltage provides a high impedance to said corresponding interconnect line in response to said both first and second signals on said corresponding I/O line.
Claim 29
Dependent Claim
169 words
A programmable connector for a programmable logic device comprising: a plurality of I/O lines; at least one interconnect line; a plurality of programmable interconnects, each corresponding to at least one of said I/O lines and one interconnect line, each of said programmable interconnects comprising: means for applying a first voltage to said interconnect line; control means for controlling said means for applying a first voltage, said control means being controlled by a signal on said at least one I/O line, means for programmably applying a signal present on one of said at least one interconnect line to one of said plurality of I/O lines, and means for programmably applying the complement of said signal present on said one of said at least one interconnect line to said one of said plurality of I/O lines; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 30
Dependent Claim
169 words
A programmable connector for a programmable logic device comprising: a plurality of I/O lines; at least one interconnect line; a plurality of programmable interconnects, each corresponding to at least one of said I/O lines and one interconnect line, each of said programmable interconnects comprising: means for applying a first voltage to said interconnect line; control means for controlling said means for applying a first voltage, said control means being controlled by a signal on said at least one I/O line, means for programmably applying a signal present on one of said at least one interconnect line to one of said plurality of I/O lines, and means for programmably applying the complement of said signal present on said one of said at least one interconnect line to said one of said plurality of I/O lines; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 31
Dependent Claim
209 words
A programmable connector for an integrated circuit comprising: a plurality of I/O lines; at least one interconnect line; a plurality of programmable interconnects, each of which corresponds to one of said I/O lines and one of said at least one interconnect line; means for operating said at least one programmable interconnect on one of three modes, comprising: means for, in a first mode, providing a high impedance to said corresponding interconnect line in response to a high signal on said corresponding I/O line, and providing a first constant voltage to said corresponding interconnect line in response to a low signal on said corresponding I/O line; means for, in a second mode, providing a high impedance to said corresponding interconnect line in response to a low signal on said corresponding I/O line, and providing said first constant voltage to said corresponding interconnect line in response to a high signal on said corresponding I/O line; and means for, in a third mode, providing one of a signal present on one of said at least one interconnect line to one of said plurality of I/O lines, and the complement of said signal present on said one of said at least one interconnect line to said one of said plurality of I/O lines.
Claim 32
Dependent Claim
209 words
A programmable connector for an integrated circuit comprising: a plurality of I/O lines; at least one interconnect line; a plurality of programmable interconnects, each of which corresponds to one of said I/O lines and one of said at least one interconnect line; means for operating said at least one programmable interconnect on one of three modes, comprising: means for, in a first mode, providing a high impedance to said corresponding interconnect line in response to a high signal on said corresponding I/O line, and providing a first constant voltage to said corresponding interconnect line in response to a low signal on said corresponding I/O line; means for, in a second mode, providing a high impedance to said corresponding interconnect line in response to a low signal on said corresponding I/O line, and providing said first constant voltage to said corresponding interconnect line in response to a high signal on said corresponding I/O line; and means for, in a third mode, providing one of a signal present on one of said at least one interconnect line to one of said plurality of I/O lines, and the complement of said signal present on said one of said at least one interconnect line to said one of said plurality of I/O lines.
Claim 33
Dependent Claim
149 words
A programmable connector for a programmable logic device comprising: at least one I/O lines; at least one interconnect line; means for segmenting at least one of said at least one interconnect line comprising at least one controllable switching means located along said at least one interconnect line; at least one programmable interconnect, each corresponding to at least one of said at least one I/O line and one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line; control means for controlling said means for applying a first voltage, said control means being controlled by a signal on said at least one I/O line; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 34
Dependent Claim
149 words
A programmable connector for a programmable logic device comprising: at least one I/O lines; at least one interconnect line; means for segmenting at least one of said at least one interconnect line comprising at least one controllable switching means located along said at least one interconnect line; at least one programmable interconnect, each corresponding to at least one of said at least one I/O line and one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line; control means for controlling said means for applying a first voltage, said control means being controlled by a signal on said at least one I/O line; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 35
Dependent Claim
232 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; at least one programmable interconnect, each corresponding to at least one of said at least one I/O line and one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line; control means for controlling said means for applying a first voltage, said control means being controlled by a signal on said at least one I/O line; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by nay of said means for applying a first voltage; said programmable connector further comprising a latch inserted between said I/O line and said programmable interconnect, said latch comprising a data port connected to said I/O line, an enable port, and an output port connected to said programmable interconnect, said output port being connected to said I/O line when a signal on said enable port has a first state and said output port being disconnected from said I/O line when a signal on said enable port has a second state, said output port providing to said programmable interconnect a signal related to a signal present on said I/O line when said signal on said enable port last had said first state.
Claim 36
Dependent Claim
232 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; at least one programmable interconnect, each corresponding to at least one of said at least one I/O line and one interconnect line, each of said at least one programmable interconnect comprising: means for applying a first voltage to said interconnect line; control means for controlling said means for applying a first voltage, said control means being controlled by a signal on said at least one I/O line; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by nay of said means for applying a first voltage; said programmable connector further comprising a latch inserted between said I/O line and said programmable interconnect, said latch comprising a data port connected to said I/O line, an enable port, and an output port connected to said programmable interconnect, said output port being connected to said I/O line when a signal on said enable port has a first state and said output port being disconnected from said I/O line when a signal on said enable port has a second state, said output port providing to said programmable interconnect a signal related to a signal present on said I/O line when said signal on said enable port last had said first state.
Claim 37
Dependent Claim
268 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; means for segmenting at least one of said at least one interconnect line comprising at least one controllable switching means located along said at least one interconnect line; at least one programmable interconnect, each corresponding to at least one of said at least one I/O line and one interconnect line, each of said at least one programmable interconnect comprising: an N-channel FET transistor having one current carrying terminal connected to said first voltage supply and another to said interconnect line, control means for controlling said transistor, comprising: a NAND gate having an output terminal connected to said control terminal of said transistor, and at least two input terminals, each receiving input from an output terminal of a programmable logic gate, one said programmable logic gate having an input terminal connected to said I/O line and another input terminal connected to a memory cell which determines whether said logic gate will pass a signal from said I/ line to said NAND gate, and another said programmable logic gate having an input terminal connected to receive the complement of a signal on said I/O line and another input terminal connected to a memory cell which determines whether said another logic gate will pass said complement of said signal from said I/O line to said NAND gate; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
Claim 38
Dependent Claim
268 words
A programmable connector for a programmable logic device comprising: at least one I/O line; at least one interconnect line; means for segmenting at least one of said at least one interconnect line comprising at least one controllable switching means located along said at least one interconnect line; at least one programmable interconnect, each corresponding to at least one of said at least one I/O line and one interconnect line, each of said at least one programmable interconnect comprising: an N-channel FET transistor having one current carrying terminal connected to said first voltage supply and another to said interconnect line, control means for controlling said transistor, comprising: a NAND gate having an output terminal connected to said control terminal of said transistor, and at least two input terminals, each receiving input from an output terminal of a programmable logic gate, one said programmable logic gate having an input terminal connected to said I/O line and another input terminal connected to a memory cell which determines whether said logic gate will pass a signal from said I/ line to said NAND gate, and another said programmable logic gate having an input terminal connected to receive the complement of a signal on said I/O line and another input terminal connected to a memory cell which determines whether said another logic gate will pass said complement of said signal from said I/O line to said NAND gate; and means for providing a second voltage to each of said at least one interconnect line on which there is no first voltage being placed by any of said means for applying a first voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-18 | 1996-02-17 | 1996-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-18 | 2000-02-17 | 2000-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-18 | 2004-02-17 | 2004-08-18 | $7700.00 | Window Closed / Lapsed |