Regenerative comparators

Claim 2

A comparator circuit, comprising: a differential input stage including first and second inputs coupled for receiving a differential input signal and having first and second outputs for providing first and second differentially related signals; a differential to single-ended converter having first and second terminals coupled for receiving said first and second differentially related signals from said differential input stage respectively while providing a single-ended output signal at an output; a first transistor having a base, an emitter and a collector, said base being coupled to said output of said differential to single-ended converter; first current supply means having an output coupled to said collector of said first transistor for providing a first current of predetermined magnitude; a first diode having an anode coupled to said collector of said first transistor and having a cathode coupled to said second input of said differential input stage; a second transistor having a base, an emitter and a collector, said base being coupled to said output of said first current supply means, said collector being coupled to a first power supply conductor; and a flip-flop circuit having first and second inputs and an output, said first input being coupled to said emitter of said first transistor, said second input being coupled to said emitter of said second transistor, said output providing an output signal of the comparator circuit.

Claim 3

The comparator circuit of claim 1 wherein said differential input stage includes: second current supply means having an output for providing a second current of predetermined magnitude; and third and fourth transistors each having a base, an emitter and a collector, said bases being coupled for receiving said differential input signal, said emitters being coupled together to said output of said second current supply means, said collectors providing said first and second differentially related signals.

Claim 4

The comparator circuit of claim 2 wherein said differential to single-ended converter includes: a second diode having an anode coupled to said collector of said third transistor and having a cathode coupled to a second power supply conductor; and a fifth transistor having a base, an emitter and a collector, said base being coupled to said anode of said second diode, said emitter being coupled to said second power supply conductor, said collector being coupled to said collector of said fourth transistor at said output of said differential to single-ended converter.

Claim 5

A comparator circuit, comprising: first and second inputs; a differential input stage comprising, a first transistor having a base terminal coupled to said first input, a second transistor having a base terminal coupled to said second input and having a further terminal providing an output, said first and second transistors being coupled to a current mirror configuration whereby said output of said differential input stage is indicative of the relative voltage levels at said first and second inputs; an intermediate stage comprising, (a) a third transistor having a base terminal coupled to said output of said differential input stage and a further terminal coupled to said base terminal of said second transistor to cause regeneration in said differential input stage during a cross-over in relative voltage levels at said first and second inputs, and (b) means for inhibiting an output change until onset of regeneration of said differential stage; and an output stage comprising flip-flop means providing an output stage output, said flip-flop means being coupled to said intermediate stage to provide said output change on said output stage output as a result of said cross-over.

Claim 6

A comparator circuit, comprising: first and second inputs; a differential input stage comprising, a first transistor having a base terminal coupled to said first input, a second transistor having a base terminal coupled to said second input and having a further terminal providing an output, said first and second transistors being coupled to a current mirror configuration whereby said output of said differential input stage is indicative of the relative voltage levels at said first and second inputs; an intermediate stage comprising, (a) a third transistor having a base terminal coupled to said output of said differential input stage and a further terminal coupled to said base terminal of said second transistor to cause regeneration in said differential input stage during a cross-over in relative voltage levels at said first and second inputs, and (b) means for inhibiting an output change until onset of regeneration of said differential stage; and an output stage comprising flip-flop means providing an output stage output, said flip-flop means being coupled to said intermediate stage to provide said output change on said output stage output as a result of said cross-over.

Claim 7

A comparator as claimed in claim 4 wherein said intermediate stage takes a first state before regeneration and a second state following onset of regeneration, said second state controlling said output stage.

Claim 8

A comparator as claimed in claim 5 wherein a state of said first and second states is a transistor off state and a state of said first and second states is a transistor saturated state.

Claim 9

A comparator as claimed in claim 4 and wherein hysteresis is provided by an offset applied to a reference voltage as an input to said differential stage in one state of said differential stage.

Claim 10

A comparator comprising: first and second inputs; a differential input stage comprising, a first transistor having a base terminal coupled to said first input, a second transistor having a base terminal coupled to said second input and having a further terminal providing an output, said first and second transistors being coupled to a current mirror configuration whereby said output of said differential input stage is indicative of the relative voltage levels at said first and second inputs; an intermediate stage comprising, (a) current source means and a third transistor having a base terminal coupled to said output of said differential input stage and a further terminal coupled to said base terminal of said second transistor and to said current source means to control supply of current from the current source means to the second transistor, said control of current being responsive to the second transistor thereby providing regeneration in said differential input stage during a cross-over in relative voltage levels at said first and second inputs, and (b) a fourth transistor in said intermediate stage responsive to the supply of current to the second transistor for inhibiting an output change until onset of regeneration of said differential stage; and an output stage comprising flip-flop means providing an output stage output, said flip-flop means being coupled to said intermediate stage to provide said output change on said output stage output as a result of said cross-over.

Claim 11

A comparator comprising: first and second inputs; a differential input stage comprising, a first transistor having a base terminal coupled to said first input, a second transistor having a base terminal coupled to said second input and having a further terminal providing an output, said first and second transistors being coupled to a current mirror configuration whereby said output of said differential input stage is indicative of the relative voltage levels at said first and second inputs; an intermediate stage comprising, (a) current source means and a third transistor having a base terminal coupled to said output of said differential input stage and a further terminal coupled to said base terminal of said second transistor and to said current source means to control supply of current from the current source means to the second transistor, said control of current being responsive to the second transistor thereby providing regeneration in said differential input stage during a cross-over in relative voltage levels at said first and second inputs, and (b) a fourth transistor in said intermediate stage responsive to the supply of current to the second transistor for inhibiting an output change until onset of regeneration of said differential stage; and an output stage comprising flip-flop means providing an output stage output, said flip-flop means being coupled to said intermediate stage to provide said output change on said output stage output as a result of said cross-over.