Latching comparator with hysteresis

Claim 2

A latching comparator circuit with hysteresis comprising: differential amplifier means having first and second inputs and first, second, third, and fourth outputs, said first and second inputs for respectively receiving input and reference signals, said differential amplifier means responsive to said input and reference signals for respectively producing first, second, third, and fourth currents at said first, second, third and fourth outputs; output circuit means coupled to said first and second outputs, said output circuit means having a fifth output and providing at said fifth output an output signal capable of assuming one or another of two states in response to said first and second currents; first latch control means coupled to said first input and said third output, said first latch control means having a first control signal input for receiving a first control signal, said first latch control means for controlling said first, second, third, and fourth currents, said first latch control means responsive to said first latch control signal such that when said input signal has a first predetermined relationship with said reference signal said output signal changes from said one of said two states to said another of said two states and prevents said output signal from changing from said another of said two states to said one of said two states; and second latch control means coupled to said second input and said fourth output, said second latch control means having a second control signal input for receiving a second control signal, said second latch control means for controlling said first, second, third, and fourth currents, said second latch control means responsive to said second latch control signal such that when said input signal has a second predetermined relationship with said reference signal said output signal changes from said another of said two states to said one of said two states and prevents said output signal from changing from said one of said two states to said another of said two states.

Claim 3

The latching comparator of claim 1 further comprising: input buffer means coupled to said first input for receiving and transmitting said input signal to said differential amplifier means wherein said input buffer means isolates said input signal from said differential amplifier means when said output signal changes from said one of said two state to said another of said two states; and reference buffer means coupled to said second input for receiving and transmitting said reference signal to said differential amplifier means wherein said reference buffer means isolates said reference signal from said differential amplifier means when said output signal changes from said another of said two states to said one of said two states.

Claim 4

The latching comparator of claim 1 further comprising time delay means coupled to said first and second control signal inputs and said fifth output, said time delay means responsive to said output signal for generating said first and second control signals.

Claim 5

The latching comparator of claim 2 further comprising time delay means coupled to said first and second control signal inputs and said fifth output, said time delay means responsive to said output signal for generating said first and second control signals.

Claim 6

The latching comparator of claim 1 wherein said first and second predetermined relationship with said reference signal are symmetrical about said reference signal.

Claim 7

A latching comparator circuit with hysteresis comprising: first and second transistors each having a base, emitter and a pair of collectors; constant current source means coupled to the emitters of said first and second transistors, said constant current source means for providing current to said first and second transistors; third and fourth transistors each having a base, emitter and collector, said third and fourth transistor base adapted to respectively receive input and reference voltages, and said third and fourth transistor collectors coupled to ground; first and second current source means respectively coupled to said third and fourth transistor emitters, said first and second current sources providing current to said third and fourth transistors; fifth and sixth transistors each having a base, emitter and collector, said fifth and sixth transistor bases and said fifth transistor collector coupled to one collector of said first transistor collector pair, said sixth transistor collector coupled to one collector of said second transistor collector pair and adapted to provide an output voltage, said fifth and sixth transistor emitters coupled to ground, seventh and eighth transistors each having a base, emitter and collector, said seventh transistor collector coupled to said first transistor base, said seventh transistor base and said eighth transistor collector coupled to the other collector of said first transistor collector pair, said eight transistor base adapted to receive a first latch control signal, and said seventh and eight transistors emitters coupled to ground; first current sinking means coupled between said seventh transistor base and ground, said first current sinking means for sinking a first predetermined amount of current to ground; ninth and tenth transistors each having abase, emitter and collector, said ninth transistor collector coupled to said second transistor base, said ninth transistor base and said tenth transistor collector coupled to the other collector of said second transistor collector pair, said tenth transistor base adapted to receive a second latch control signal, and said ninth and tenth transistor emitters coupled to ground; and second current sinking means coupled between said ninth transistor base and ground, said second current sinking means for sinking a second predetermined amount of current to ground.

Claim 8

A latching comparator circuit with hysteresis comprising: first and second transistors each having a base, emitter and a pair of collectors; constant current source means coupled to the emitters of said first and second transistors, said constant current source means for providing current to said first and second transistors; third and fourth transistors each having a base, emitter and collector, said third and fourth transistor base adapted to respectively receive input and reference voltages, and said third and fourth transistor collectors coupled to ground; first and second current source means respectively coupled to said third and fourth transistor emitters, said first and second current sources providing current to said third and fourth transistors; fifth and sixth transistors each having a base, emitter and collector, said fifth and sixth transistor bases and said fifth transistor collector coupled to one collector of said first transistor collector pair, said sixth transistor collector coupled to one collector of said second transistor collector pair and adapted to provide an output voltage, said fifth and sixth transistor emitters coupled to ground, seventh and eighth transistors each having a base, emitter and collector, said seventh transistor collector coupled to said first transistor base, said seventh transistor base and said eighth transistor collector coupled to the other collector of said first transistor collector pair, said eight transistor base adapted to receive a first latch control signal, and said seventh and eight transistors emitters coupled to ground; first current sinking means coupled between said seventh transistor base and ground, said first current sinking means for sinking a first predetermined amount of current to ground; ninth and tenth transistors each having abase, emitter and collector, said ninth transistor collector coupled to said second transistor base, said ninth transistor base and said tenth transistor collector coupled to the other collector of said second transistor collector pair, said tenth transistor base adapted to receive a second latch control signal, and said ninth and tenth transistor emitters coupled to ground; and second current sinking means coupled between said ninth transistor base and ground, said second current sinking means for sinking a second predetermined amount of current to ground.

Claim 9

The latching comparator circuit of claim 6 wherein said first, second, third, and fourth transistors are of the PNP type and said fifth, sixth, seventh, eighth, ninth, and tenth transistors are of the NPN type.

Claim 10

The latching comparator circuit of claim 6 wherein said first and second current sinking means are each capable of sinking to ground an amount of current up to a predetermined amount of current, said predetermined amount of current being in the range of about one-twenty second to one-fourth the amount of current provided by said constant current source means.

Claim 11

The latching comparator circuit of claim 8 wherein said first and second current sinking means are each capable of sinking to ground an amount of current up to about one-third the amount of current provided by said constant current source means.

Claim 12

The latching comparator circuit of claim 9 wherein said first and second current source means are each capable of providing an amount of current up to about two-thirds the amount of current provided by said constant current source means.

Claim 13

The latching comparator circuit of claim 6 further comprising delay means having a control input coupled to said sixth transistor collector and having first and second control outputs respectively coupled to said eighth and tenth transistor bases, said delay means for, while in a first condition with said output signal in one of two output states, generating said first control signal of one of said two control states and said second control signal of another of said two control states, said delay means changing to a second condition after a predetermined period of time of said output signal changing to another of said two output states, said delay means for, while in said second condition, generating said first control signal of said another of said two control states and said second control signal of said one of said two control states, said delay means changing to said first condition after a second predetermined period of time of said output signal changing to said one of said two output states.

Claim 14

A latching comparator circuit with hysteresis comprising: first and second transistors each having a base, emitter and collector; constant current source means coupled to the emitters of said first and second transistors, said constant current source means for providing current to said first and second transistors; third and fourth transistors each having a base, emitter and collector, said third and fourth transistor emitters respectively coupled to said first and second transistor bases, said third and fourth transistor bases adapted to respectively receive input and reference voltages, and said third and fourth transistor collectors coupled to ground; first and second current source means respectively coupled to said third and fourth transistor emitters for providing current to said third and fourth transistors; fifth, sixth, seventh, and eighth transistors each having a base, emitter and collector, said fifth and sixth transistor collectors coupled to said constant current source means, said fifth and sixth transistor bases respectively coupled to said first and second transistor bases, said fifth and sixth transistor emitters respectively coupled to said seventh and eighth transistor collectors, said seventh transistor collector coupled to said seventh and eighth transistor bases, said eighth transistor collector adapted to provide an output voltage, said seventh and eight transistor emitters coupled to ground; ninth and tenth transistors each having a base, emitter and collector, said ninth transistor collector coupled to said first transistor base, said ninth transistor base and said tenth transistor collector coupled to said first transistor collector, said tenth transistor base adapted to receive a first latch control signal, and said ninth and tenth transistors emitters coupled to ground; first current sinking means coupled between said ninth transistor base and ground, said first current sinking means for sinking a first predetermined amount of current to ground; eleventh and twelfth transistors each having a base, emitter and collector, said eleventh transistor collector coupled to said second transistor base, said eleventh transistor base and said twelfth transistor collector coupled to said second transistor collector, said twelfth transistor base adapted to receive a second latch control signal, and said eleventh and twelfth transistor emitters coupled to ground; and second current sinking means coupled between said eleventh transistor base and ground, said second current sinking means for sinking a second predetermined amount of current to ground.

Claim 15

A latching comparator circuit with hysteresis comprising: first and second transistors each having a base, emitter and collector; constant current source means coupled to the emitters of said first and second transistors, said constant current source means for providing current to said first and second transistors; third and fourth transistors each having a base, emitter and collector, said third and fourth transistor emitters respectively coupled to said first and second transistor bases, said third and fourth transistor bases adapted to respectively receive input and reference voltages, and said third and fourth transistor collectors coupled to ground; first and second current source means respectively coupled to said third and fourth transistor emitters for providing current to said third and fourth transistors; fifth, sixth, seventh, and eighth transistors each having a base, emitter and collector, said fifth and sixth transistor collectors coupled to said constant current source means, said fifth and sixth transistor bases respectively coupled to said first and second transistor bases, said fifth and sixth transistor emitters respectively coupled to said seventh and eighth transistor collectors, said seventh transistor collector coupled to said seventh and eighth transistor bases, said eighth transistor collector adapted to provide an output voltage, said seventh and eight transistor emitters coupled to ground; ninth and tenth transistors each having a base, emitter and collector, said ninth transistor collector coupled to said first transistor base, said ninth transistor base and said tenth transistor collector coupled to said first transistor collector, said tenth transistor base adapted to receive a first latch control signal, and said ninth and tenth transistors emitters coupled to ground; first current sinking means coupled between said ninth transistor base and ground, said first current sinking means for sinking a first predetermined amount of current to ground; eleventh and twelfth transistors each having a base, emitter and collector, said eleventh transistor collector coupled to said second transistor base, said eleventh transistor base and said twelfth transistor collector coupled to said second transistor collector, said twelfth transistor base adapted to receive a second latch control signal, and said eleventh and twelfth transistor emitters coupled to ground; and second current sinking means coupled between said eleventh transistor base and ground, said second current sinking means for sinking a second predetermined amount of current to ground.

Claim 16

The latching comparator circuit of claim 12 wherein said first, second, third, and fourth transistors are of the PNP type and said fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors are of the NPN type.

Claim 17

The latching comparator circuit of claim 12 wherein said first and second current sinking means are each capable of sinking to ground an amount of current up to a predetermined amount of current, said predetermined amount of current being in the range of about one-twenty-second to one-fourth the amount of current provided by said constant current source means.

Claim 18

The latching comparator circuit of claim 14 wherein said first and second current sinking means are each capable of sinking to ground an amount of current up to about one-third the amount of current provided by said constant current source means.

Claim 19

The latching comparator circuit of claim 15 wherein said first and second current source means are each capable of providing an amount of current up to about two-thirds the amount of current provided by said constant current source means.

Claim 20

The latching comparator circuit of claim 12 further comprising delay means having a control input coupled to said eighth transistor collector and having first and second control outputs respectively coupled to said tenth and twelfth transistor bases, said delay means for, while in a first condition with said output signal in one of two output states, generating said first control signal of one of two control states and said second control signal of another of said two control states, said delay means changing to a second condition after a first predetermined period of time of said output signal changing to another of said two output states, said delay means for, while in said second condition, generating said first control signal of said another of said two controls states and said second control signal of said one of said two control states, said delay means changing to said first condition after a second predetermined perod of time of said output signal changing to said one of said two output states.