Patent US5140176A successfully refreshed from Google Patents.
US5140176A
Expired / Lapsed
US
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Sequential logic circuit device
Assignee: Advantest Corp
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Filing: 1991-03-07
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Granted: 1992-08-18
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Expires: 2011-03-07
Abstract
Abstract A logic circuit part, which is composed of a flip-flop group and a combinational circuit and performs a sequential logic operation, is added with a specify circuit for selectively specifying desired flip-flop circuits in the flip-flop group and a write circuit for applying a set or reset signal to the flip-flop circuits selectively specified by the specify circuit. Each flip-flop circuit includes: a flip-flop for writing input data in response to a system clock; a first AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the set signal to set the flip-flop; a second AND gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the reset signal to reset the flip-flop; and a third and gate which, when the flip-flop circuit is selectively specified by the specify circuit, passes therethrough the output logic of the flip-flop to the outside.
Inventors
- 👤 Noboru Okino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:28
CPC Classifications
H; H03; H03K; H03K19/00; G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G05B19/0423; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/284
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
204 words
A sequential logic circuit device comprising: a logic circuit part composed of a flip-flop group including a plurality of flip-flop circuits and a combinatorial circuit connected to said flip-flop group, for performing a predetermined sequential logic operation; specify circuit means for selectively specifying said flip-flop circuits in said flip-flop group in accordance with an external address, said specify circuit means including decoder means for decoding said address and applying a decoded address signal to each said flip-flop circuit selectively specified in said flip-flop group; and write circuit means whereby set or reset signals are applied to said flip-flop circuits selectively specified by said specify circuit means, in accordance with an external setting signal; wherein each of said flip-flop circuits in said flip-flop group includes; flip-flop means for storing logic input data; first gate means responsive to said decoded address signal to apply said set signal to said flip-flop means to set said flip-flop means; second gate means responsive to said decoded address signal and cleared by an external clear signal to apply said reset signal to said flip-flop means to reset said flip-flop means; and third gate means for externally outputting the logic in said flip-flop means in response to said decoded address signal.
Claim 2
Dependent Claim
204 words
A sequential logic circuit device comprising: a logic circuit part composed of a flip-flop group including a plurality of flip-flop circuits and a combinatorial circuit connected to said flip-flop group, for performing a predetermined sequential logic operation; specify circuit means for selectively specifying said flip-flop circuits in said flip-flop group in accordance with an external address, said specify circuit means including decoder means for decoding said address and applying a decoded address signal to each said flip-flop circuit selectively specified in said flip-flop group; and write circuit means whereby set or reset signals are applied to said flip-flop circuits selectively specified by said specify circuit means, in accordance with an external setting signal; wherein each of said flip-flop circuits in said flip-flop group includes; flip-flop means for storing logic input data; first gate means responsive to said decoded address signal to apply said set signal to said flip-flop means to set said flip-flop means; second gate means responsive to said decoded address signal and cleared by an external clear signal to apply said reset signal to said flip-flop means to reset said flip-flop means; and third gate means for externally outputting the logic in said flip-flop means in response to said decoded address signal.
Claim 3
Dependent Claim
19 words
The sequential logic circuit device of claim 1, wherein said first, second and third gate means are AND gates.
Claim 4
Dependent Claim
34 words
The sequential logic circuit device of claim 2, wherein said flip-flop means of said each flip-flop circuit is a D type flip-flop which stores said input data in response to an external system clock.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-18 | 1996-02-17 | 1996-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-18 | 2000-02-17 | 2000-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-18 | 2004-02-17 | 2004-08-18 | $7700.00 | Window Closed / Lapsed |