US5140174A
Expired / Lapsed
US
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Symmetric edge true/complement buffer/inverter and method therefor
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1991-01-25
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Granted: 1992-08-18
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Expires: 2011-01-25
Abstract
Abstract The present invention is directed to a buffer/inverter which generates symmetric and complementary output signals from a single input signal. The device employs four inverters having similar switching speeds. The true output signal is generated by passing the input signal through two inverters. The complement output signal is generated by passing the true output signal through a third inverter, passing the input signal through a fourth inverter and coupling the outputs of the third and fourth inverters.
Inventors
- 👤 Peter Meier
- 👤 Ken DelGrande
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:52
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
170 words
A buffer/inverter that receives an input signal and generates first and second output signals which are symmetric and complementary, which buffer/inverter comprises: (a) a first inverter having an input terminal and an output terminal, said input terminal being connected to receive the input signal; (b) a second inverter having an input terminal and an output terminal, said input terminal of said second inverter being connected to said output terminal of said first inverter, and said output terminal of said second inverter being connected to produce the first output signal; (c) a third inverter having an input terminal and an output terminal, said input terminal of said third inverter being connected to said output terminal of said second inverter; (d) a fourth inverter having an input terminal and an output terminal, said input terminal of said fourth inverter being connected to receive the input signal; and (e) said output terminal of said third inverter and said output terminal of said fourth inverter being coupled together to generate the second output signal.
Claim 2
Dependent Claim
170 words
A buffer/inverter that receives an input signal and generates first and second output signals which are symmetric and complementary, which buffer/inverter comprises: (a) a first inverter having an input terminal and an output terminal, said input terminal being connected to receive the input signal; (b) a second inverter having an input terminal and an output terminal, said input terminal of said second inverter being connected to said output terminal of said first inverter, and said output terminal of said second inverter being connected to produce the first output signal; (c) a third inverter having an input terminal and an output terminal, said input terminal of said third inverter being connected to said output terminal of said second inverter; (d) a fourth inverter having an input terminal and an output terminal, said input terminal of said fourth inverter being connected to receive the input signal; and (e) said output terminal of said third inverter and said output terminal of said fourth inverter being coupled together to generate the second output signal.
Claim 3
Dependent Claim
19 words
The buffer/inverter of claim 1, wherein said first, second, third and fourth inverters are formed on the same chip.
Claim 4
Dependent Claim
18 words
The buffer/inverter of claim 2, wherein said first, second, third and fourth inverters are of similar switching speeds.
Claim 5
Dependent Claim
16 words
The buffer/inverter of claim 3, wherein said first, second, third and fourth inverters are CMOS devices.
Claim 6
Independent Claim
131 words
A system for generating from an input signal a first output signal and a second output signal which is symmetric and complementary to the first output signal, comprising: (a) a first inverting means for delaying and inverting the input signal so as to generate a first intermediate signal; (b) a second inverting means for delaying and inverting said first intermediate signal so as to generate the first output signal; (c) a third inverting means for delaying and inverting the first output signal so as to generate a second intermediate signal; (d) a fourth inverting means for delaying and inverting the input signal so as to generate a third intermediate signal; and (e) a coupling means for coupling said second and third intermediate signals so as to generate the second output signal.
Claim 7
Independent Claim
131 words
A system for generating from an input signal a first output signal and a second output signal which is symmetric and complementary to the first output signal, comprising: (a) a first inverting means for delaying and inverting the input signal so as to generate a first intermediate signal; (b) a second inverting means for delaying and inverting said first intermediate signal so as to generate the first output signal; (c) a third inverting means for delaying and inverting the first output signal so as to generate a second intermediate signal; (d) a fourth inverting means for delaying and inverting the input signal so as to generate a third intermediate signal; and (e) a coupling means for coupling said second and third intermediate signals so as to generate the second output signal.
Claim 8
Dependent Claim
19 words
The system of claim 5, wherein any of said first, second, third and fourth inverting means is an inverter.
Claim 9
Dependent Claim
20 words
The system of claim 5, wherein any of said first, second, third and fourth inverting means is a NAND gate.
Claim 10
Dependent Claim
20 words
The system of claim 5, wherein any of said first, second, third and fourth inverting means is a NOR gate.
Claim 11
Dependent Claim
20 words
The system of claim 5, wherein any of said first, second, third and fourth inverting means is a AND-OR-invert gate.
Claim 12
Dependent Claim
20 words
The system of claim 5, wherein any of said first, second, third and fourth inverting means is a OR-AND-invert gate.
Claim 13
Dependent Claim
20 words
The system of claim 5, wherein said first, second, third and fourth inverting means are formed on a single chip.
Claim 14
Dependent Claim
17 words
The system of claim 5, wherein said first, second, third and fourth inverting means are CMOS devices.
Claim 15
Dependent Claim
23 words
The system of claim 5, wherein said first, second, third and fourth inverting means have a switching speed which is substantially the same.
Claim 16
Dependent Claim
29 words
The system of claim 5, wherein said coupling means is an electrical connection between an output of said third inverting means and an output of said fourth inverting means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-18 | 1996-02-17 | 1996-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-18 | 2000-02-17 | 2000-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-18 | 2004-02-17 | 2004-08-18 | $7700.00 | Window Closed / Lapsed |