Patent US5138515A successfully refreshed from Google Patents.
US5138515A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse-controlled gate circuit with protection against short-circuit
Assignee: STMicroelectronics SA
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Filing: 1991-04-24
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Granted: 1992-08-11
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Expires: 2011-04-24
Abstract
Abstract A pulse-controlled circuit for an insulate gate power transistor (Tp) comprises an auxiliary MOS transistor (T1) connected between the gate and a reference terminal of the power transformer in parallel with a pulse transformer secondary (W2). This circuit comprises two controlled unidirectionally conductive paths in parallel (D1, M1; D2, M2) between one terminal of the transformer secondary and the auxiliary transistor gate, these paths being alternatively rendered conductive when a positive or negative pulse is applied to the secondary of the transformer.
Inventors
- 👤 Jean-Marie Bourgeois
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:58
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/0406; H03K17/51; H03K17/56; H03K17/687; H03K17/689; H03K17/691
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
143 words
A pulse-controlled circuit for a power transistor with an insulated gate, having a first gate terminal and a second reference terminal, comprising an auxiliary MOS transistor connected between said first and second terminals, a pulse transformer secondary having third and fourth terminals coupled to the first and second terminals, a first diode connected between said second and fourth terminals, and two controlled unidirectionally conductive paths in parallel, between said fourth terminal and said auxiliary transistor gate, said paths being alternatively rendered conductive when a positive or negative pulse is applied to said secondary of the transformer, wherein said paths respectively comprise a second and a third diode in series with a first and a second MOS transistor, said second and third diodes being anti-parallel connected, said MOS transistors being of the opposite channel-type, their gates being interconnected and coupled to said third terminal.
Claim 2
Dependent Claim
143 words
A pulse-controlled circuit for a power transistor with an insulated gate, having a first gate terminal and a second reference terminal, comprising an auxiliary MOS transistor connected between said first and second terminals, a pulse transformer secondary having third and fourth terminals coupled to the first and second terminals, a first diode connected between said second and fourth terminals, and two controlled unidirectionally conductive paths in parallel, between said fourth terminal and said auxiliary transistor gate, said paths being alternatively rendered conductive when a positive or negative pulse is applied to said secondary of the transformer, wherein said paths respectively comprise a second and a third diode in series with a first and a second MOS transistor, said second and third diodes being anti-parallel connected, said MOS transistors being of the opposite channel-type, their gates being interconnected and coupled to said third terminal.
Claim 3
Dependent Claim
69 words
A control circuit according to claim 1, further comprising means for interrupting the conduction of the power transistor when its load is shorted, wherein said interruption means comprise a path in parallel with said first diode, said path being switched on when the current in the power transistor exceeds a predetermined intensity or when the voltage drop at the conductive state in said power transistor exceeds a predetermined value.
Claim 4
Dependent Claim
49 words
A control circuit according to claim 2, wherein said path comprises a fourth diode reversely connected with respect to said first diode and a third MOS transistor, the gate of which is connected to said second terminal, said second terminal being connected to a load through a measure resistor.
Claim 5
Dependent Claim
24 words
A control circuit according to claim 3, comprising means for inhibiting the conduction of said path during charging of the power transistor gate capacitance.
Claim 6
Dependent Claim
78 words
A control circuit according to claim 4, wherein said inhibition means comprise a fourth and a fifth MOS transistor, said fourth MOS transistor being connected to the terminals of said measure resistor through a further resistor, said fifth MOS transistor being connected between the gate of said fourth MOS transistor and said third terminal, the gate of said fifth MOS transistor being connected to said first terminal and an impedance being connected between said first and third terminals.
Claim 7
Dependent Claim
47 words
A control circuit according to claim 2, wherein the primary of said transformer is associated with a circuit for detecting the passage of a pulse discharging the gate/electrode capacitance of the power transistor Tp in the secondary of the transformer after the switching on of said path.
Claim 8
Dependent Claim
52 words
A control circuit according to claim 6, wherein the primary of the transformer is energized by a bridge connection, said detection circuit being associated with a leg of the bridge which is at the conductive state once the power transistor has been controlled through a pulse to be in the conductive state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |