Three terminal bidirectional source to source FET circuit

Claim 2

A bidirectional FET circuit comprising: first and second enhancement mode FETs connected source to source in series relation between first and second power switching terminals, current conduction in one direction traversing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain pn junction of said second FET, and current conduction in the opposite direction traversing through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain pn junction off said first FET; and current source means for supplying a constant fixed level of current independent of input voltage, and including resistance means, connected to the gates of said FETs for driving them into conduction; wherein said resistance means comprises a resistor having one end connected to a node connecting said FET sources, and having the other end connected to a node connecting said current source and a node connecting said FET gate, such that the gate to source potential for each FET is the product of the current through said resistor from said current source means and the resistance value of said resistor, regardless of the polarity of the corresponding power switching terminal.

Claim 3

The invention according to claim 1 wherein said current source means comprises a source follower FET connected between said other end of said resistor and a switch control terminal for receiving a control potential, said last mentioned FET having its gate connected to one of said power switching terminals, one of its drain and source connected to said other end of said resistor, and the other of its drain and source connected to said switch control terminal.

Claim 4

The invention according to claim 2 wherein: said power switching terminals are connectable to the series connection of an AC power source and a load, with one of said power switching terminals referenced to ground; said switch control terminal is connectable to a source of gate voltage referenced to ground; and said last mentioned FET comprises a p channel MOSFET having its gate connected to ground, its drain connected to said other end of said resistor, and its source connected to said switch control terminal.

Claim 5

The invention according to claim 1 wherein said current source means comprises a current mirror.

Claim 6

The invention according to claim 1 wherein said current source means comprises a zener diode regulated current source.

Claim 7

A three terminal bidirectional FET circuit comprising: first and second enhancement mode FETs connected source to source in series relation between first and second power switching terminals, said terminals being connectable to the series connection of an AC power source and a load, current conduction in one direction traversing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain pn junction of said second FET, and current conduction in the opposite direction traversing through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain pn junction of said first FET; current source means for supplying a constant fixed level of current independent of input voltage, connected between the gates of said FETs and a switch control terminal; resistance means connected between a node connecting said FET sources and a node connecting said FET gates, such that the gate to source voltage for each FET is the same regardless of the polarity of one said power switching terminal relative to the other; wherein said current source means comprises a source follower mode grounded gate FET connected between said switch control terminal and a node connecting said resistance means and said FET gates, said last mentioned FET having its gate referenced to ground, one of its drain and source connected to said node connecting said resistance means and said FET gates, and the other of its drain and source connected to said switch control terminal.

Claim 8

A three terminal bidirectional FET circuit comprising: first and second enhancement mode FETs connected source to source in series relation between first and second power switching terminals, said terminals being connectable to the series connection of an AC power source and a load, current conduction in one direction traversing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain pn junction of said second FET, and current conduction in the opposite direction traversing through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain pn junction of said first FET; current source means for supplying a constant fixed level of current independent of input voltage, connected between the gates of said FETs and a switch control terminal; resistance means connected between a node connecting said FET sources and a node connecting said FET gates, such that the gate to source voltage for each FET is the same regardless of the polarity of one said power switching terminal relative to the other; wherein said current source means comprises a source follower mode grounded gate FET connected between said switch control terminal and a node connecting said resistance means and said FET gates, said last mentioned FET having its gate referenced to ground, one of its drain and source connected to said node connecting said resistance means and said FET gates, and the other of its drain and source connected to said switch control terminal.

Claim 9

A three terminal bidirectional FET circuit comprising: first and second enhancement mode FETs connected source to source in series relation between first and second power switching terminals, said terminals being connectable to the series connection of an AC power source and a load, current conduction in one direction traversing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain pn junction of said second FET, and current conduction in the opposite direction traversing through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain pn junction of said first FET; current source means for supplying a constant fixed level of current independent of input voltage, connected between the gates of said FETs and a switch control terminal; resistance means connected between a node connecting said FET sources and a node connecting said FET gates, such that the gate to source voltage for each FET is the same regardless of the polarity of one said power switching terminal relative to the other; fast turn-off circuitry for said FETs, comprising transistor means biased into conduction by removal of gate drive from said switch control terminal and by residual stored charge in the gate to source capacitance of said FETs, said transistor means in a conductive state draining said residual charge from said FET gates.

Claim 10

A three terminal bidirectional FET circuit comprising: first and second enhancement mode FETs connected source to source in series relation between first and second power switching terminals, said terminals being connectable to the series connection of an AC power source and a load, current conduction in one direction traversing through the series connection of the drain-source current path of said first FET and the forward biased substrate-drain pn junction of said second FET, and current conduction in the opposite direction traversing through the series connection of the drain-source current path of said second FET and the forward biased substrate-drain pn junction of said first FET; current source means for supplying a constant fixed level of current independent of input voltage, connected between the gates of said FETs and a switch control terminal; resistance means connected between a node connecting said FET sources and a node connecting said FET gates, such that the gate to source voltage for each FET is the same regardless of the polarity of one said power switching terminal relative to the other; fast turn-off circuitry for said FETs, comprising transistor means biased into conduction by removal of gate drive from said switch control terminal and by residual stored charge in the gate to source capacitance of said FETs, said transistor means in a conductive state draining said residual charge from said FET gates.

Claim 11

The invention according to claim 7 wherein said transistor means comprises a pair of regeneratively coupled bipolar transistors driven into latched conduction by the residual stored charge on said FET gates in combination with the absence of gate current from said switch control terminal.

Claim 12

The invention according to claim 8 wherein said bipolar transistors comprise a first PNP transistor having its emitter connected to said node connecting said FET gates and having its base connected to said current source means, and an NPN transistor having its base connected to the collector of said PNP transistor, its collector connected to the base of said PNP transistor, and its emitter connected to said node connecting said FET sources.

Claim 13

The invention according to claim 7 wherein said transistor means of said fast turn-off circuitry comprises a pair of bipolar transistors connected in Darlington relation between said node connecting said FET gates and said node connecting said FET sources, and having one of their emitter and collector connected to said node connecting said FET gates, and the other of their emitter and collector connected to said node connecting said FET sources, and having a base connected to said current source means.

Claim 14

The invention according to claim 10 wherein said Darlington transistor pair comprises a first PNP transistor having its emitter connected to said node connecting said FET gates and its collector connected to said node connecting said FET sources, and a second PNP transistor having its emitter connected to the base of said first PNP transistor, its base connected to said current source means, and its collector connected to said node connecting said FET sources.

Claim 15

The invention according to claim 6 further comprising fast turn-off circuitry for said FETs, comprising transistor means biased into conduction by removal of gate drive from said switch control terminal and by residual stored charge in the gate to source capacitance of said FETs, said transistor means in a conductive state draining said residual charge from said FET gates.

Claim 16

The invention according to claim 12 wherein said transistor means comprises a pair of regeneratively coupled bipolar transistors driven into latched conduction by the residual stored charge on said FET gates in combination with the absence of gate current from said switch control terminal, said bipolar transistors comprising a first PNP transistor having its emitter connected to said node connecting said FET gates and having its base connected to the drain of said source follower mode grounded gate FET, and comprising an NPN transistor having its base connected to the collector of said PNP transistor, its collector connected to the base of said PNP transistor, and its emitter connected to said node connecting said FET sources.

Claim 17

The invention according to claim 12 wherein said transistor means of said fast turn-off circuitry comprises a pair of bipolar transistors connected in Darlington relation between said node connecting said FET gates and said node connecting said FET sources, and having a base connected to the drain of said source follower mode grounded gate FET, said Darlington transistor pair comprising a first PNP transistor having its emitter connected to said node connecting said FET gates and its collector connected to said node connecting said FET sources, and comprising a second PNP transistor having its emitter connected to the base of said first PNP transistor, its base connected to said drain of said source follower mode grounded gate FET, and its collector connected to said node connecting said FET sources.

Claim 18

The invention according to claim 7 wherein said current source means comprises a current mirror.