Piso electrostatic discharge protection device

Claim 2

A semiconductor protection circuit comprising: a semiconductor substrate of a first conductivity type; a first region of a second conductivity type formed in said substrate at a surface thereof; a first region of said first conductivity type formed in said first region of said second conductivity type and having a different degree of conductivity from said semiconductor substrate; a second region of said first conductivity type formed in said first region of said first conductivity type and having a higher degree of conductivity than said first region of said first conductivity type; and a second region of said second conductivity type formed in said first region of said second conductivity type and having a higher degree of conductivity than said first region of said second conductivity type, said second region of said second conductivity type being connected to said second region of said first conductivity type.

Claim 3

A semiconductor protection circuit in accordance with claim 1, wherein said first region of said first conductivity type is doped at a concentration such that a junction between said second region of said second conductivity type and said first region of said first conductivity type exhibits a smaller reverse breakdown voltage than is exhibited by a junction between said second region of said second conductivity type and said semiconductor substrate.

Claim 4

A semiconductor protection circuit in accordance with claim 2, wherein said junction between said second region of said second conductivity type and said first region of said first conductivity type exhibits a reverse breakdown voltage in the order of 14 Volts, and wherein said junction between said second region of said second conductivity type and said semiconductor substrate exhibits a reverse breakdown voltage of in the order of 22 Volts.

Claim 5

A semiconductor protection circuit in accordance with claim 1, wherein said first region of said first conductivity type is doped at a concentration such that a junction between said second region of said second conductivity type and said first region of said first conductivity type exhibits a reverse breakdown voltage smaller by an amount in the order of 8 Volts than is exhibited by a junction between said second region of said second conductivity type and said semiconductor substrate.

Claim 6

A semiconductor protection circuit in accordance with claim 9, comprising: a third region of said first semiconductor type formed in said semiconductor substrate.

Claim 7

A semiconductor protection circuit in accordance with claim 5, wherein said second region of said first conductivity type is connected to terminal and said third region of said first semiconductor type is connected to a point of reference potential.

Claim 8

A semiconductor protection circuit in accordance with claim 1, wherein a space charge region of said semiconductor substrate and said first region of said first conductivity type touch before avalanche breakdown takes place between said first region of said second conductivity type and said semiconductor substrate.

Claim 9

A semiconductor protection circuit in accordance with claim 7, wherein said space charge regions of said semiconductor substrate and said first region of said first conductivity type touch at about 11.0 volts, and the avalanche breakdown between said first region of said second conductivity type and said semiconductor substrate occurs at about 45.0 volts.

Claim 10

A semiconductor protection circuit comprising: a semiconductor substrate of P conductivity type; a region of N conductivity type formed in said semiconductor substrate at a surface thereof: a region of P type isolation region (PISO region), as utilized in the CMOS 3 and CMOS 3.5 processes, formed in said region of N conductivity type; a first region of P+ conductivity type formed in said PISO region; a region of N+ conductivity type formed in said region of N conductivity type, said first region of P+ conductivity type and said region of N+ conductivity type being connected to a terminal; and a second region of P+ conductivity type formed in said semiconductor substrate, said second region of P+ conductivity type being connected to a point of reference potential.

Claim 11

A semiconductor protection circuit comprising: a semiconductor substrate of P conductivity type; a region of N conductivity type formed in said semiconductor substrate at a surface thereof: a region of P type isolation region (PISO region), as utilized in the CMOS 3 and CMOS 3.5 processes, formed in said region of N conductivity type; a first region of P+ conductivity type formed in said PISO region; a region of N+ conductivity type formed in said region of N conductivity type, said first region of P+ conductivity type and said region of N+ conductivity type being connected to a terminal; and a second region of P+ conductivity type formed in said semiconductor substrate, said second region of P+ conductivity type being connected to a point of reference potential.

Claim 12

A semiconductor protection circuit comprising: a semiconductor substrate of P conductivity type; a region of N conductivity type formed in said semiconductor substrate at a surface thereof; a first region of P type isolation region (PISO region), as utilized in the CMOS 3 and CMOS 3.5 processes, formed in said region of N conductivity type; a first region of P+ conductivity type formed in said first PISO region; a first region of N+ conductivity type formed in said region of N conductivity type; a second region of P+ conductivity type formed in said semiconductor substrate; a second region of said P type isolation region (PISO region), as utilized in the CMOS 3 and CMOS 3.5 processes, formed in said substrate at said surface thereof; a second region of N+ conductivity type formed in said second PISO region; a third region of P+ conductivity type formed partly in each of said semiconductor substrate and said second PISO region so as to bridge a junction therebetween; and a third region of N+ conductivity type formed in said second PISO region in a location intermediate said third region of P+ conductivity type and said second region of N+ conductivity type.

Claim 13

A semiconductor protection circuit comprising: a semiconductor substrate of P conductivity type; a region of N conductivity type formed in said semiconductor substrate at a surface thereof; a first region of P type isolation region (PISO region), as utilized in the CMOS 3 and CMOS 3.5 processes, formed in said region of N conductivity type; a first region of P+ conductivity type formed in said first PISO region; a first region of N+ conductivity type formed in said region of N conductivity type; a second region of P+ conductivity type formed in said semiconductor substrate; a second region of said P type isolation region (PISO region), as utilized in the CMOS 3 and CMOS 3.5 processes, formed in said substrate at said surface thereof; a second region of N+ conductivity type formed in said second PISO region; a third region of P+ conductivity type formed partly in each of said semiconductor substrate and said second PISO region so as to bridge a junction therebetween; and a third region of N+ conductivity type formed in said second PISO region in a location intermediate said third region of P+ conductivity type and said second region of N+ conductivity type.

Claim 14

A semiconductor protection circuit as recited in claim 10, wherein said first and second regions of P type isolation region (PISO region) are formed by ion implantation of boron at in the order of 60 keV, 2.0 E13/cm 2 , 1.0-1.1 μm deep.

Claim 15

A semiconductor protection circuit as recited in claim 10, wherein said first region of P+ conductivity type, said first region of N+ conductivity type, and said second region of N+ conductivity type are connected to a terminal; and said second region of P+ conductivity type, said third region of P+ conductivity type, and said third region of N+ conductivity type are connected to a point of reference potential.