US5138195A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bi-CMOS logic circuit having full voltage swing and rapid turn-off
Assignee: Fujitsu Ltd
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Filing: 1990-10-19
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Granted: 1992-08-11
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Expires: 2010-10-19
Abstract
Abstract A Bi-CMOS logic circuit includes first and second bipolar transistors connected in series between a first power source and a second power source. An output signal is drawn from a connection node at which first and second bipolar transistors are connected in series. The Bi-CMOS logic circuit also includes a first impedance element, connected between a base and an emitter of the first bipolar transistor, providing a first impedance, and a second impedance element, connected between a base of the second bipolar transistor and an emitter thereof, providing a second impedance. Further, the Bi-CMOS logic circuit includes a first MOS transistor connected between the collector of the first bipolar transistor and the base thereof, a second MOS transistor connected between the collector of the second bipolar transistor and the base thereof, an input signal being applied to gates of the first and second MOS transistors; and a third MOS transistor connected between the base of the first bipolar transistor and the second power source. The third MOS transistor has the gate thereof connected to the base of the second bipolar transistor.
Inventors
- 👤 Shinzou Satou
- 👤 Kou Ebihara
- 👤 Toru Nakamura
- 👤 Toshiyuki Koreeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
171 words
A Bi-CMOS logic circuit comprising: first and second bipolar transistors connected in series between a first power source and a second power source, an output signal being drawing from a connection node at which said first and second bipolar transistors are connected in series; first impedance means, connected between the base and the emitter of said first bipolar transistor, for providing a first impedance; second impedance means, connected between the base of said second bipolar transistor and the emitter thereof, for providing a second impedance; a first MOS transistor connected between the collector of said first bipolar transistor and the base thereof; a second MOS transistor connected between the collector of said second bipolar transistor and the base thereof, an input signal being applied in common to the gates of said first and second MOS transistors; and a third MOS transistor connected between the base of said first bipolar transistor and said second power source, said third MOS transistor having a gate connected to the base of said second bipolar transistor.
Claim 2
Dependent Claim
171 words
A Bi-CMOS logic circuit comprising: first and second bipolar transistors connected in series between a first power source and a second power source, an output signal being drawing from a connection node at which said first and second bipolar transistors are connected in series; first impedance means, connected between the base and the emitter of said first bipolar transistor, for providing a first impedance; second impedance means, connected between the base of said second bipolar transistor and the emitter thereof, for providing a second impedance; a first MOS transistor connected between the collector of said first bipolar transistor and the base thereof; a second MOS transistor connected between the collector of said second bipolar transistor and the base thereof, an input signal being applied in common to the gates of said first and second MOS transistors; and a third MOS transistor connected between the base of said first bipolar transistor and said second power source, said third MOS transistor having a gate connected to the base of said second bipolar transistor.
Claim 3
Dependent Claim
33 words
A Bi-CMOS logic circuit as claimed in claim 1, wherein each of said second and third MOS transistors is an N-channel MOS transistor, and said first MOS transistor is a P-channel MOS transistor.
Claim 4
Dependent Claim
21 words
A Bi-CMOS logic circuit as claimed in claim 1, wherein each of said first and second impedance means comprises a resistor.
Claim 5
Dependent Claim
203 words
A Bi-CMOS logic circuit comprising: first and second bipolar transistors connected in series between a first power source and a second power source, an output signal being drawn from a connection node at which said first and second bipolar transistors are connected in series; first impedance means, connected between the base and the emitter of said first bipolar transistor, for providing a first impedance; second impedance means, connected between the base of said second bipolar transistor and the emitter thereof, for providing a second impedance; a first group of n MOS transistors connected in parallel between the base and collector of said first bipolar transistor where n is an integer, said n MOS transistors of the first group having respective gates respectively receiving n corresponding input signals; a second group of n MOS transistors connected in series between the base and the collector of said second bipolar transistor, said n MOS transistors of said second group having respective gates respectively receiving said corresponding n input signals; and a discharge MOS transistor connected between the base of said first bipolar MOS transistor and said second power source, said discharge MOS transistor having the gate thereof connected to the base of said second bipolar transistor.
Claim 6
Dependent Claim
203 words
A Bi-CMOS logic circuit comprising: first and second bipolar transistors connected in series between a first power source and a second power source, an output signal being drawn from a connection node at which said first and second bipolar transistors are connected in series; first impedance means, connected between the base and the emitter of said first bipolar transistor, for providing a first impedance; second impedance means, connected between the base of said second bipolar transistor and the emitter thereof, for providing a second impedance; a first group of n MOS transistors connected in parallel between the base and collector of said first bipolar transistor where n is an integer, said n MOS transistors of the first group having respective gates respectively receiving n corresponding input signals; a second group of n MOS transistors connected in series between the base and the collector of said second bipolar transistor, said n MOS transistors of said second group having respective gates respectively receiving said corresponding n input signals; and a discharge MOS transistor connected between the base of said first bipolar MOS transistor and said second power source, said discharge MOS transistor having the gate thereof connected to the base of said second bipolar transistor.
Claim 7
Dependent Claim
42 words
A Bi-CMOS logic circuit as claimed in claim 1, wherein said n MOS transistors of the first group are respectively P-channel MOS transistors, and said n MOS transistors of the second group and said discharge MOS transistor are respectively N-channel MOS transistors.
Claim 8
Dependent Claim
21 words
A Bi-CMOS logic circuit as claimed in claim 4, wherein each of said first and second impedance means comprises a resistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |