Methods and apparatus for caching interlock variables in an integrated cache memory

Claim 2

A cache memory for caching interlock variables in a computing system including: plural central processing units ("CPUs"), processor bus means for coupling signals between said CPUs and the cache memory, a main memory having plural regions, and memory bus means for coupling signals between said main memory and the cache memory, the cache memory comprising: (a) a processor bus interface; (b) a memory bus interface; (c) a processor bus unit coupled between the processor bus means and the processor bus interface for controlling the processor bus interface; (d) a memory bus unit coupled between the memory bus means and the memory bus interface for controlling the memory bus interface; and (e) a cache unit coupled to both said processor bus unit and said memory bus unit for caching interlock variables, means supplying the cached interlock variables to said plural processing units via said processor bus means and to certain of said plural regions of main memory for interlocking said plural regions of main memory and for synchronizing access to said plural processors so operations of said plural processors are synchronized with operations of the cache unit.

Claim 3

The cache memory of claim 1 wherein said cache unit is programmable in response to signals from at least one of said processing units, said cache unit including a set of special registers for selecting programmable options, one of said options being a cache interlock enable, selection of the cache interlock enable causing the interlock variables to be cached by the cache unit.

Claim 4

The cache memory of claim 1 wherein the interlock variable guarantees exclusive access from one of said processors to said cache memory.

Claim 5

The cache memory of claim 2 wherein said programmable cache unit includes memory array means.

Claim 6

The cache memory of claim 4 wherein said memory array means stores cached data and instruction signals and is organized as a set of blocks, each block corresponding to a predetermined number of cached words.

Claim 7

The cache memory of claim 5 wherein said programmable cache unit supports variable block and sub-block sizing.

Claim 8

A cache memory for caching interlock variables in a computing system including: plural central processing units ("CPUs"), processor bus means for coupling signals between said CPUs and the cache memory, a main memory having plural regions, and memory bus means for coupling signals between said main memory and the cache memory, the cache memory comprising: (a) a processor bus interface; (b) a memory bus interface; (c) a processor bus unit coupled between the processor bus means and the processor bus interface for controlling the processor bus interface; (d) a memory bus unit coupled between the memory bus means and the memory bus interface for controlling the memory bus interface; and (e) a cache unit coupled to both said processor bus unit and said memory bus unit for caching interlock variables, means supplying the cached interlock variables to said plural processing units via said processor bus means and to certain of said plural regions of main memory for interlocking said plural regions of main memory and for synchronizing access to said plural processors so operations of said plural processors are synchronized with operations of the cache unit; said cache unit being programmable in response to signals from at least one of said processing units, said cache unit including a set of special registers for selecting programmable options, one of said options being a cache interlock enable, selection of the cache interlock enable causing the interlock variables to be cached by the cache unit, said programmable cache unit including memory array means which, in a first configuration, is located within said programmable cache means and which, in a second configuration, is located outside said programmable cache means, said memory array means storing cached data and instruction signals and being organized as a set of blocks, each block corresponding to a predetermined number of cached words, said programmable cache unit supporting variable block and sub-block sizing, said programmable cache unit further comprising: (a) a cache unit address bus, coupled to said processor bus unit and said memory bus unit, for carrying address signals; (b) a cache unit data bus, coupled to said processor bus unit and said memory bus unit, for carrying data signals; (c) block status array means coupled to said cache data bus, for storing an indication of the modified, shared and locked status of each block; and (d) cache unit control means, coupled to said processor bus control means and said memory bus control means, for synchronizing and controlling operations of (i) said programmable cache unit, (ii) said processor bus unit, (iii) said memory bus unit, and (iv) said plural processors.

Claim 9

A cache memory for caching interlock variables in a computing system including: plural central processing units ("CPUs"), processor bus means for coupling signals between said CPUs and the cache memory, a main memory having plural regions, and memory bus means for coupling signals between said main memory and the cache memory, the cache memory comprising: (a) a processor bus interface; (b) a memory bus interface; (c) a processor bus unit coupled between the processor bus means and the processor bus interface for controlling the processor bus interface; (d) a memory bus unit coupled between the memory bus means and the memory bus interface for controlling the memory bus interface; and (e) a cache unit coupled to both said processor bus unit and said memory bus unit for caching interlock variables, means supplying the cached interlock variables to said plural processing units via said processor bus means and to certain of said plural regions of main memory for interlocking said plural regions of main memory and for synchronizing access to said plural processors so operations of said plural processors are synchronized with operations of the cache unit; said cache unit being programmable in response to signals from at least one of said processing units, said cache unit including a set of special registers for selecting programmable options, one of said options being a cache interlock enable, selection of the cache interlock enable causing the interlock variables to be cached by the cache unit, said programmable cache unit including memory array means which, in a first configuration, is located within said programmable cache means and which, in a second configuration, is located outside said programmable cache means, said memory array means storing cached data and instruction signals and being organized as a set of blocks, each block corresponding to a predetermined number of cached words, said programmable cache unit supporting variable block and sub-block sizing, said programmable cache unit further comprising: (a) a cache unit address bus, coupled to said processor bus unit and said memory bus unit, for carrying address signals; (b) a cache unit data bus, coupled to said processor bus unit and said memory bus unit, for carrying data signals; (c) block status array means coupled to said cache data bus, for storing an indication of the modified, shared and locked status of each block; and (d) cache unit control means, coupled to said processor bus control means and said memory bus control means, for synchronizing and controlling operations of (i) said programmable cache unit, (ii) said processor bus unit, (iii) said memory bus unit, and (iv) said plural processors.

Claim 10

The cache memory of claim 7 wherein said cache control means is further operative to generate hit signals for valid cache accesses and maintains and updates data stored in said set of special registers and said block status array.

Claim 11

The cache memory of claim 8 further comprising means for treating the interlock variables as non-cachable in response to one of said processors deriving a signal indicating that said cache interlock enable option has not been selected.

Claim 12

The cache memory of claim 9 further comprising means for transferring an access to an interlock varaible to said memory bus with a lock indication in response to said interlock variables being non-cachable.

Claim 13

The cache memory of claim 8 further comprising means for indicating that a processor access is an interlocked access.

Claim 14

The cache memory of claim 11 further comprising means, coupled to said memory bus interface, for indicating that a memory access is an interlocked access.

Claim 15

The cache memory of claim 12 further comprising means for locking a variable for exclusive use of a specified one of said processors.

Claim 16

The cache memory of claim 13 wherein said set of special registers includes at least one programmable register having at least one bit for selecting a 2 n way set associative cache organization where n is an integer greater than or equal to zero.

Claim 17

The cache memory of claim 8 further comprising means for testing interlocked variables.

Claim 18

The cache memory of claim 15 including means responsive to said cache enable option being selected and no hit occurring in a shared block for treating an interlocked read as a miss, starting a reload operation on said memory bus, generating a lock indication signal and storing the read data in a cache memory block which is thereafter assigned as shared.

Claim 19

The cache memory of claim 16 including means responsive to an interlocked read occurring with a hit in a shared block for supplying data from a cache memory with no memory bus access.

Claim 20

The cache memory of claim 16 including means responsive to a said cache enable option being selected for treating an interlocked write operation as a function of the state of a processor generated lock indication signal supplied by said processor in a cycle preceding a write access.

Claim 21

The cache memory of claim 18 including means responsive to said lock indication signal being in a first state for initiating a write-through operation to said memory.

Claim 22

The cache memory of claim 19 including means responsive to said lock indication signal being in a second state for writing data into said memory array means.

Claim 23

The cache memory of claim 20 including means for writing data to said main memory in response to a prior read access generating a miss so that the main memory is written into only while the interlocked variable is read the first time.

Claim 24

The cache memory of claim 21 further comprising means for supplying a lock indication signal to said memory during memory write operations.

Claim 25

The cache memory of claim 22, wherein the processor bus interface, memory bus interface, processor bus unit, memory bus unit, and cache unit are integrated on a single chip.

Claim 26

The cache memory of claim 15 wherein the cache memory is configured to operate as a cache master.

Claim 27

The cache memory of claim 24 wherein the cache master derives a signal via said shared means for indicating memory bus accesses in response to an interlocked access being derived on said memory bus.

Claim 28

The cache memory of claim 25 further comprising means for releasing interlocked variables.

Claim 29

The cache memory of claim 26 wherein said means for releasing interlocked variables further comprises means for invalidating cache variables so that subsequent processor accesses are a miss and so that the most recent value of the variable is read from main memory.

Claim 30

The cache memory of claim 27, wherein the processor bus interface, memory bus interface, processor bus unit, memory bus unit, and cache unit are integrated on a single chip.

Claim 35

A method as set forth in claim 30 further comprising the steps of generating hit signals for valid cache accesses and maintaining and updating data stored in said set of special registers and said block status array, via said cache control means.

Claim 36

A method as set forth in claim 31 further comprising the step of treating interlock variables as non-cachable in response to said cache interlock enable option not being selected.

Claim 37

A method as set forth in claim 32 further comprising the steps of transferring an access to an interlock variable to said memory bus and generating a lock indication signal in response to said interlock variables being non-cachable.

Claim 38

A method as set forth in claim 32 further comprising the step of generating a first signal in response to a processor access being an interlocked access.

Claim 39

A method as set forth in claim 34 further comprising the step of generating a second signal in response to a memory access being an interlocked access.

Claim 40

A method as set forth in claim 35 further comprising the step of locking a variable for exclusive use of a specified one of said processors.

Claim 41

A method as set forth in claim 31 further comprising testing the interlocked variables.

Claim 42

A method as set forth in claim 37, further comprising the steps of: (a) treating an interlocked read as a miss; (b) starting a reload operation on said memory bus; (c) generating a lock indication signal; and (d) storing the read stat in a cache memory array block which is thereafter assigned as shared, steps (a), (b), (c) and (d) being performed in response to said cache enable option being selected and no hit occurring in a shared block.

Claim 43

A method as set forth in claim 38 further comprising the step of supplying data from the cache memory array with no memory bus access in response to interlocked read occurring with a hit in a shared block.

Claim 44

A method as set forth in claim 38 further comprising the step of treating an interlocked write operation as a function of the state of a processor generated lock indication signal derived by one of said processors in the cycle preceding the write access in response to said cache enable option being selected.

Claim 45

A multiprocessor system comprising a cache memory unit for caching interlock variables, plural central processing units ("CPUs"), processor bus means for coupling signals between one of said CPUs and the cache memory unit, a main memory having plural regions, and memory bus means for coupling signals between said main memory and the cache memory unit, the cache memory unit comprising: (a) a processor bus interface; (b) a memory bus interface; (c) a processor bus unit coupled between the processor bus means and the processor bus interface for controlling the processor bus interface; (d) a memory bus unit coupled between the memory bus means and the memory bus interface for controlling the memory bus interface; and (e) a cache unit coupled to both said processor bus unit and said memory bus unit for caching interlock variables, means supplying the cached interlock variables to said plural processing units via said processor bus means and to certain of said plural regions of main memory for interlocking said plural regions of main memory and for synchronizing access to said plural processors so operations of said plural processors are synchronized with operations of the cache memory unit.

Claim 46

A multiprocessor system comprising a cache memory unit for caching interlock variables, plural central processing units ("CPUs"), processor bus means for coupling signals between one of said CPUs and the cache memory unit, a main memory having plural regions, and memory bus means for coupling signals between said main memory and the cache memory unit, the cache memory unit comprising: (a) a processor bus interface; (b) a memory bus interface; (c) a processor bus unit coupled between the processor bus means and the processor bus interface for controlling the processor bus interface; (d) a memory bus unit coupled between the memory bus means and the memory bus interface for controlling the memory bus interface; and (e) a cache unit coupled to both said processor bus unit and said memory bus unit for caching interlock variables, means supplying the cached interlock variables to said plural processing units via said processor bus means and to certain of said plural regions of main memory for interlocking said plural regions of main memory and for synchronizing access to said plural processors so operations of said plural processors are synchronized with operations of the cache memory unit.

Claim 47

The multiprocessor system of claim 41 wherein said cache unit is programmable in response to signals from at least one of said processing units, said cache unit including a set of special registers for selecting programmable options, one of said options being a cache interlock enable, selection of the cache interlock enable causing the interlock variables to be cached by the cache unit.

Claim 48

The multiprocessor system of claim 41 wherein the interlock variable guarantees exclusive access from one of said processors to said cache memory.

Claim 49

The multiprocessor system of claim 41 wherein each processor includes software for examining the interlock variable of the cache unit.

Claim 50

A multiprocessor system comprising a cache memory unit for caching interlock variables, plural central processing units ("CPUs"), processor bus means for coupling signals between one of said CPUs and the cache memory unit, a main memory having plural regions, and memory bus means for coupling signals between said main memory and the cache memory unit, the cache memory unit comprising: (a) a processor bus interface; (b) a memory bus interface; (c) a processor bus unit coupled between the processor bus means and the processor bus interface for controlling the processor bus interface; (d) a memory bus unit coupled between the memory bus means and the memory bus interface for controlling the memory bus interface; (e) a cache unit coupled to both said processor bus unit and said memory bus unit for caching interlock variables, means supplying the cached interlock variables to said plural processing units via said processor bus means and to certain of said plural regions of main memory for interlocking said plural regions of main memory and for synchronizing access to said plural processors so operations of said plural processors are synchronized with operations of the cache memory unit, said programmable cache unit including: (a) a cache unit address bus, coupled to said processor bus unit and said memory bus unit, for carrying address signals; (b) a cache unit data bus, coupled to said processor bus unit and said memory bus unit, for carrying data signals; (c) block status array means coupled to said cache data bus, for storing an indication of the modified, shared and locked status of each block; and (d) cache unit control means, coupled to said processor bus control means and said memory bus control means, for synchronizing and controlling operations of (i) said programmable cache unit, (ii) said processor bus unit, (iii) said memory bus unit and said plural processors.

Claim 51

A multiprocessor system comprising a cache memory unit for caching interlock variables, plural central processing units ("CPUs"), processor bus means for coupling signals between one of said CPUs and the cache memory unit, a main memory having plural regions, and memory bus means for coupling signals between said main memory and the cache memory unit, the cache memory unit comprising: (a) a processor bus interface; (b) a memory bus interface; (c) a processor bus unit coupled between the processor bus means and the processor bus interface for controlling the processor bus interface; (d) a memory bus unit coupled between the memory bus means and the memory bus interface for controlling the memory bus interface; (e) a cache unit coupled to both said processor bus unit and said memory bus unit for caching interlock variables, means supplying the cached interlock variables to said plural processing units via said processor bus means and to certain of said plural regions of main memory for interlocking said plural regions of main memory and for synchronizing access to said plural processors so operations of said plural processors are synchronized with operations of the cache memory unit, said programmable cache unit including: (a) a cache unit address bus, coupled to said processor bus unit and said memory bus unit, for carrying address signals; (b) a cache unit data bus, coupled to said processor bus unit and said memory bus unit, for carrying data signals; (c) block status array means coupled to said cache data bus, for storing an indication of the modified, shared and locked status of each block; and (d) cache unit control means, coupled to said processor bus control means and said memory bus control means, for synchronizing and controlling operations of (i) said programmable cache unit, (ii) said processor bus unit, (iii) said memory bus unit and said plural processors.