MOSFET with substrate source contact

Claim 2

A vertical MOSFET device comprising: a semiconductor substrate having first and second opposed surfaces; a drain region adjacent the first surface, a channel forming region underlying the drain region, a source region underlying the channel forming region and a gate dielectric and electrode on a portion of the channel forming region between the source and drain regions for modulating the conductivity therebetween; and a buried ohmic contact shorting part of the channel forming region to the underlying source region.

Claim 3

The device of claim 1 wherein the buried ohmic contact is formed in a cavity extending from the first surface into the substrate and having a sidewall portion which is inclined so that a PN junction between the channel forming region and the source may be viewed when looking into the cavity.

Claim 4

The device of claim 1 further comprising a drift region between the channel forming region and the drain region.

Claim 5

The device of claim 1 further comprising a source contact extending to the second surface and a drain contact extending to the first surface.

Claim 6

The device of claim 1 wherein the buried ohmic contact is formed in a first cavity extending from the first surface into the substrate.

Claim 7

The device of claim 5 wherein the gate dielectric and electrode are formed on the sidewalls of a second cavity extending from the first surface into the substrate.

Claim 8

A semiconductor device comprising: a semiconductor substrate having first and second opposed principal surfaces; a vertical MOSFET in the substrate, having source, drain, and gate for forming a channel permitting current flow between a source contact on the second surface and a drain contact on the first surface; and a buried ohmic contact within the substrate shorting the source to part of an internal region of the substrate in which the channel is formed.

Claim 9

A semiconductor device comprising: a semiconductor substrate having first and second opposed principal surfaces; a vertical MOSFET in the substrate, having source, drain, and gate for forming a channel permitting current flow between a source contact on the second surface and a drain contact on the first surface; and a buried ohmic contact within the substrate shorting the source to part of an internal region of the substrate in which the channel is formed.

Claim 10

The semiconductor device of claim 7 wherein the vertical MOSFET is formed in a first cavity extending from the first surface into the substrate.

Claim 11

The semiconductor device of claim 8 wherein the buried ohmic contact is formed in a second cavity extending from the first surface into the substrate.

Claim 12

A semiconductor device comprising: a first semiconductor region of a first conductivity and type; a second semiconductor region on the first semiconductor region and of a second conductivity and of a second type opposite the first type; a third semiconductor region on the second semiconductor region and of a third conductivity and of the first type; a fourth semiconductor region in the third semiconductor region and of a fourth conductivity and of the first type and extending to an upper surface of the third region; a first cavity having first and second sidewalls extending from the upper surface to the first region, wherein portions of the first and second regions are exposed in the first cavity; a first dielectric on a first portion of the second region exposed in the first cavity; a conductor on a first portion of the first region and a second portion of the second region exposed in the first cavity and ohmically contacting the first and second regions but not the third region; and a gate electrode on a second dielectric formed on the sidewalls of a second cavity extending from the upper surface to the first region, a source electrode contacting the first region and a drain electrode contacting the fourth region.

Claim 13

A semiconductor device comprising: a first semiconductor region of a first conductivity and type; a second semiconductor region on the first semiconductor region and of a second conductivity and of a second type opposite the first type; a third semiconductor region on the second semiconductor region and of a third conductivity and of the first type; a fourth semiconductor region in the third semiconductor region and of a fourth conductivity and of the first type and extending to an upper surface of the third region; a first cavity having first and second sidewalls extending from the upper surface to the first region, wherein portions of the first and second regions are exposed in the first cavity; a first dielectric on a first portion of the second region exposed in the first cavity; a conductor on a first portion of the first region and a second portion of the second region exposed in the first cavity and ohmically contacting the first and second regions but not the third region; and a gate electrode on a second dielectric formed on the sidewalls of a second cavity extending from the upper surface to the first region, a source electrode contacting the first region and a drain electrode contacting the fourth region.

Claim 14

The device of claim 10 wherein the second cavity has a "V" shaped bottom.