← Back to Patent Explorer
US5130941A Expired / Lapsed US ⏱️ 0.0 years remaining

Dynamic barrel shifter

Assignee: Toshiba Corp
•
Filing: 1990-12-06
•
Granted: 1992-07-14
•
Expires: 2010-12-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A dynamic barrel shifter has a data input portion, a data shift portion, and a shifted data output portion including sense inverters which are set at threshold voltage higher than a half of the power source voltage. The sense inverters are provided for every transmission route for each binary code. The dynamic barrel shifter also has a pre-charge portion for pre-charging the data shift portion and the shifted data output portion prior to the input of data. The pre-charge portion includes a first power source voltage applying circuit for applying electric potential lower than the power source voltage to the data shift portion through first gate elements from the power source, and a second power source voltage applying circuit for applying electric potential equal to the power source voltage to the input side of the shifted data output portion through second gate elements.

Inventors

  • 👤 Tsuneaki Kudou

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 17:33
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/38; G06; G06F; G06F5/00; G06F5/01; G06F5/015

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 257 words
A dynamic barrel shifter for shifting input data with binary codes transmitted through a plurality of N channel transistors connected by first-data-transmission routes, comprising: first pre-charging means for pre-charging the first-data-transmission routes to a preset high level with a first electric potential of less than a supply electric potential, through an N channel transistor before shifting the input data; second pre-charging means for pre-charging second-data-transmission routes which follow the first-data-transmission routes to the supply electric potential, through a P channel transistor before shifting the input data, the second-data-transmission routes thereby being preset at the high level; input data shifting means for shifting the input data by a shift count in response to shift control signals by discharging the first-data-transmission routes and the second-data-transmission routes in cases where the input data is at a low level and by maintaining the charges of both the first-data-transmission routes and the second-data-transmission routes in cases where the input data is at the high level; and input data output means with sense inverters for outputting the input data shifted by the input data shifting means after inverting the shifted input data at the high level in the sense inverters when the supply electric potential of the second-data-transmission routes is decreased to a value lower than that of a threshold voltage of the sense inverter, the threshold voltage being higher than half of the supply electric potential, and after inverting the shifted input data at the low level in the sense inverters when the second-data-transmission routes are maintained at the supply electric potential.
Claim 2
Dependent Claim 257 words
A dynamic barrel shifter for shifting input data with binary codes transmitted through a plurality of N channel transistors connected by first-data-transmission routes, comprising: first pre-charging means for pre-charging the first-data-transmission routes to a preset high level with a first electric potential of less than a supply electric potential, through an N channel transistor before shifting the input data; second pre-charging means for pre-charging second-data-transmission routes which follow the first-data-transmission routes to the supply electric potential, through a P channel transistor before shifting the input data, the second-data-transmission routes thereby being preset at the high level; input data shifting means for shifting the input data by a shift count in response to shift control signals by discharging the first-data-transmission routes and the second-data-transmission routes in cases where the input data is at a low level and by maintaining the charges of both the first-data-transmission routes and the second-data-transmission routes in cases where the input data is at the high level; and input data output means with sense inverters for outputting the input data shifted by the input data shifting means after inverting the shifted input data at the high level in the sense inverters when the supply electric potential of the second-data-transmission routes is decreased to a value lower than that of a threshold voltage of the sense inverter, the threshold voltage being higher than half of the supply electric potential, and after inverting the shifted input data at the low level in the sense inverters when the second-data-transmission routes are maintained at the supply electric potential.
Claim 3
Dependent Claim 120 words
A dynamic barrel shifter according to claim 1, wherein each sense inverter in the input data outputting means comprises: an N channel transistor for transmitting a zero electric potential from a source thereof to a drain in cases where a binary code set to the supply electric potential is transmitted to a gate thereof; and a P channel transistor, having a drain coupled to the drain of the N channel transistor, for transmitting the supply electric potential from a source thereof to the drain thereof in cases where a binary code set to a zero electric potential is transmitted to a gate thereof, the electric capacity of the P channel transistor being larger than that of the N channel transistor.
Claim 4
Dependent Claim 130 words
A dynamic barrel shifter according to claim 1, wherein each sense inverter in the shifted data output means comprises: a plurality of N channel transistors connected with each other in series for transmitting a zero electric potential from a connected source thereof to a connected drain in cases where one binary code set to the supply electric potential is transmitted to gates thereof; and a P channel transistor having a drain coupled to the connected drain of the N channel transistors for transmitting the supply electric potential from a source thereof to the drain thereof in cases where a binary code set to a zero electric potential is transmitted to a gate thereof, the electric capacity of the P channel transistor being larger than that of the N channel transistors.
Claim 5
Dependent Claim 28 words
The dynamic barrel shifter recited in claim 1, wherein said N channel transistors present a back gate effect and said P channel transistors present no back gate effect.

References Cited (Backward Citations)

DE3513473A1 Cited
US4653019A Cited
WO1988000738A2 Cited
US4831571A Cited
US4839839A Cited
US4839840A Cited
US4962511A Cited
US4999796A Cited
US5024993A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-07-14 1996-01-13 1996-07-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-07-14 2000-01-13 2000-07-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-07-14 2004-01-13 2004-07-14 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag