Superconducting-semiconducting circuits, devices and systems

Claim 2

A superconducting-semiconducting electrical circuit element comprising: (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions; and (b) a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from said superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from said superconducting device.

Claim 3

The circuit element of claim 1, wherein said superconducting charge controlled device comprises a superconducting field-effect transistor having a superconducting source, a superconducting drain, a conducting gate, and a semiconducting channel, and wherein the drain to source current is controlled by the applied gate to source voltage.

Claim 4

The circuit element of claim 1, wherein said cryogenic semiconducting interconnect circuit comprises a semiconductor inverter circuit.

Claim 5

The circuit element of claim 3, wherein said semiconductor inverter circuit further comprises a biasing means for biasing said inverter to a voltage level slightly less than the input voltage threshold of said inverter at the edge of the transition zone of the voltage transfer characteristic.

Claim 6

The circuit element of claim 4, wherein said biasing means further comprises: a bias voltage source; and calibration means for incrementally applying bias voltage to said inverter from said bias voltage source.

Claim 7

The circuit element of claim 5, wherein said calibration means further comprises a bias voltage disabling means for terminating the incremental biasing of said inverter at the edge of the transition zone of the voltage transfer characteristic.

Claim 8

The circuit element of claim 4, wherein said biasing means further comprises means for maintaining the bias voltage applied to the input of said inverter.

Claim 9

The circuit element of claim 4, wherein said inverter is of the type having an input capacitance, and wherein said biasing means comprises means for charging the input capacitance to a voltage level slightly less than the transition zone of the voltage transfer characteristic.

Claim 10

The circuit element of claim 8, wherein said calibration means comprises: a. a voltage source for providing a periodic pulse voltage output signal; and b. a semiconductor, three-terminal switching element having an input gate terminal, a voltage supply terminal, and an output terminal, wherein said gate terminal is provided the periodic pulse voltage signal as an input gate control signal, said voltage supply terminal is connected to said bias voltage means, and said output terminal is connected to the input of said semiconductor inverter circuit.

Claim 11

The circuit element of claim 9, wherein said three-terminal switching element comprises a semiconductor field effect transistor.

Claim 12

The circuit element of claim 6, wherein said bias voltage disabling means comprises a three-terminal switching element, having an input gate terminal, an output terminal and a disabling voltage terminal, and wherein said gate terminal receives the output voltage signal from said inverter as an input gate control signal, said disabling voltage terminal is held at a disabling voltage level, and said output terminal is provided as a biasing voltage disabling signal to terminate the incremental biasing of said inverter in response to a change in state of the output voltage from said inverter.

Claim 13

The circuit element of claim 11, wherein said bias voltage disabling means comprises a semiconductor field effect transistor.

Claim 14

The circuit element of claim 7, wherein said means for maintaining the bias voltage on said inverter comprises a cryogenic semiconductor three-terminal switching element, comprised of alternatively doped semiconductor elements, said three-terminal switching element having an input gate terminal, a voltage supply terminal, and an output terminal, wherein said gate terminal is provided with a bias enabling signal, said voltage supply terminal is connected to said bias voltage source, and said output terminal is connected to the input of said semiconductor inverter circuit.

Claim 15

The circuit element of claim 1, wherein said superconducting charge controlled device comprises a Josephson Junction device.

Claim 16

The circuit element of claim 2, wherein said superconducting field-effect transistor has a superconducting gate.

Claim 17

A superconducting-semiconducting electrical circuit element comprising: (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions; and (b) a voltage transducer adapted to receive as an input signal a signal formed in the output stage of said superconducting charge controlled device, and for providing a semiconductor switching level voltage output signal in response to changes in state of the output signal from said superconducting charge controlled device.

Claim 18

A superconducting-semiconducting electrical circuit element comprising: (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions; and (b) a voltage transducer adapted to receive as an input signal a signal formed in the output stage of said superconducting charge controlled device, and for providing a semiconductor switching level voltage output signal in response to changes in state of the output signal from said superconducting charge controlled device.

Claim 19

The circuit element of claim 1, wherein said superconducting charge controlled element and said cryogenic semiconducting circuit are fabricated in a monolithic integrated circuit.

Claim 20

A digital selector network formed of a plurality of superconducting-semiconducting electrical circuit elements, each of said elements comprising: (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions; and (b) a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from said superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from said superconducting device.

Claim 21

A digital selector network formed of a plurality of superconducting-semiconducting electrical circuit elements, each of said elements comprising: (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions; and (b) a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from said superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from said superconducting device.

Claim 22

The digital selector network of claim 18, wherein: the control terminals of said plurality of circuit elements are selectively coupled to a series of logic control signals designated A, A', B, B'; the second terminals of said plurality of circuit elements are selectively coupled to a series of input signals S 0 , S 1 , S 2 , S 3 ; and the third terminals of said plurality of circuit elements are coupled to a common output terminal having a value designated as the variable Z, so as to satisfy the following logic function: Z=S.sub.0 A'B'+S.sub.1 A'B+S.sub.2 AB'+S.sub.3 AB.

Claim 23

A digital barrel shifter circuit of the type adapted to permit the rotation or shifting of the contents of data present on a plurality of bus lines B i into data lines D i under control of a plurality of control signals S i , said shifter circuit being comprised of a plurality of superconductor-semiconductor electrical circuit elements, each of said circuit elements comprising: (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions; and (b) a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from said superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from said superconducting device; and (c) wherein said control terminals of said circuit elements are selectively coupled to said control signals S i , said second terminals of said circuit elements are selectively coupled to said bus lines B i , and said third terminals of said circuit elements are selectively coupled to said data lines D i .

Claim 24

A digital barrel shifter circuit of the type adapted to permit the rotation or shifting of the contents of data present on a plurality of bus lines B i into data lines D i under control of a plurality of control signals S i , said shifter circuit being comprised of a plurality of superconductor-semiconductor electrical circuit elements, each of said circuit elements comprising: (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions; and (b) a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from said superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from said superconducting device; and (c) wherein said control terminals of said circuit elements are selectively coupled to said control signals S i , said second terminals of said circuit elements are selectively coupled to said bus lines B i , and said third terminals of said circuit elements are selectively coupled to said data lines D i .