Highly responsive barrel shifter

Claim 2

A barrel shifter for shifting an input data in response to each of shift signals, respectively, by a given shift count through a plurality of series-connected semiconductor switching elements arranged between an input terminal and an output terminal thereof, which comprises: (a) means for precharging the output terminal to a supply voltage level before shifting an input data; and (b) means for turning off a rearmost semiconductor switching element when the input data is at a high level, in order to output the precharged supply voltage through the output terminal as a high level shifted output data and for turning on the same rearmost semiconductor switching element when the input data is at a low level, in order to output a ground voltage from the same output terminal as a low level shifted output data, irrespective of a threshold voltage of the semiconductor switching element.

Claim 3

The barrel shifter as set forth in claim 1, wherein said output terminal precharging means comprises a semiconductor element for applying a supply voltage to the output terminal when turned on in response to a precharge signal.

Claim 4

The barrel shifter as set forth in claim 1, wherein said rearmost switching element turning-on or -off means comprises: (a) an AND gate for providing an AND product of a shift signal and an inverted precharge signal and outputting an ANDed signal when the precharge signal is absent; and (b) a semiconductor element connected to the rearmost switching element for turning off the rearmost switching element in response to the ANDed signal when the input data is at a high level, to output the precharged supply voltage as a high level shifted output data and for turning on the rearmost switching element in response to the ANDed signal when the input data is at a low level, to output a ground level voltage as a low level shifted output data.

Claim 5

A barrel shifter for shifting an input data in response to each of shift signals, respectively by a given shift count through a plurality of MOS transistors connected in series between an input terminal and an output terminal thereof, which comprises; (a) means for precharging a drain terminal of a rearmost MOS transistor to a supply voltage level before shifting operation; and (b) means for applying a voltage, substantially equal to that given to a source terminal of the rearmost MOS transistor when the input data is at a high level, to a gate terminal of the rearmost MOS transistor, in order to turn off the rearmost MOS transistor and thereby to output the precharged supply voltage from the output terminal as a high level shifted output data, the rearmost MOS transistor being turned on when the input data is at a low level to output a ground voltage level from the output terminal as a low level shifted output data.

Claim 6

A barrel shifter for shifting an input data in response to each of shift signals, respectively by a given shift count through a plurality of MOS transistors connected in series between an input terminal and an output terminal thereof, which comprises; (a) means for precharging a drain terminal of a rearmost MOS transistor to a supply voltage level before shifting operation; and (b) means for applying a voltage, substantially equal to that given to a source terminal of the rearmost MOS transistor when the input data is at a high level, to a gate terminal of the rearmost MOS transistor, in order to turn off the rearmost MOS transistor and thereby to output the precharged supply voltage from the output terminal as a high level shifted output data, the rearmost MOS transistor being turned on when the input data is at a low level to output a ground voltage level from the output terminal as a low level shifted output data.

Claim 7

The barrel shifter as set forth in claim 4, wherein said drain terminal precharging means is a PMOS transistor turned on in response to a precharge signal to apply the supply voltage to the drain of the rearmost MOS transistor.

Claim 8

The barrel shifter as set forth in claim 4, wherein said voltage applying means comprises: (a) an AND gate for providing an AND product of a shift signal and an inversed precharge signal and outputting an ANDed signal when the precharge signal is absent; and (b) an NMOS transistor turned on in response to the ANDed signal to apply the supply voltage to the gate terminal of the rearmost MOS transistor.

Claim 9

A barrel shifter for shifting an input data in response to each of shift signals, respectively by a given shift count through a plurality of NMOS transistors connected in series between an input terminal and an output terminal thereof, which comprises: (a) a first MOS transistor having a gate terminal responsive to a precharge signal, a source terminal connected to a supply voltage, and a drain terminal connected to a drain terminal of a rearmost series-connected MOS transistor, to apply the supply voltage to the drain of the rearmost MOS transistor in response to the precharge signal; (b) an AND gate having a first input terminal connected to an inversed precharge signal and a second input terminal connected to a shift signal, to output an ANDed signal; and (c) a second MOS transistor having a gate terminal connected to the supply voltage, a source terminal connected to an output terminal of said AND gate, and a drain terminal connected to a gate of the rearmost MOS transistor, to turn off the rearmost MOS transistor by applying a voltage, substantially equal to that given to a source terminal of the rearmost MOS transistor when the input data is at a high level, in order to output the precharged supply voltage from the drain terminal of the rearmost MOS transistor as a high level shifted output data, said second MOS transistor being turned on in response to the ANDed signal when the input data is set at a low level, to output a ground level voltage from the source output terminal as a low level shifted output data.

Claim 10

A barrel shifter for shifting an input data in response to each of shift signals, respectively by a given shift count through a plurality of NMOS transistors connected in series between an input terminal and an output terminal thereof, which comprises: (a) a first MOS transistor having a gate terminal responsive to a precharge signal, a source terminal connected to a supply voltage, and a drain terminal connected to a drain terminal of a rearmost series-connected MOS transistor, to apply the supply voltage to the drain of the rearmost MOS transistor in response to the precharge signal; (b) an AND gate having a first input terminal connected to an inversed precharge signal and a second input terminal connected to a shift signal, to output an ANDed signal; and (c) a second MOS transistor having a gate terminal connected to the supply voltage, a source terminal connected to an output terminal of said AND gate, and a drain terminal connected to a gate of the rearmost MOS transistor, to turn off the rearmost MOS transistor by applying a voltage, substantially equal to that given to a source terminal of the rearmost MOS transistor when the input data is at a high level, in order to output the precharged supply voltage from the drain terminal of the rearmost MOS transistor as a high level shifted output data, said second MOS transistor being turned on in response to the ANDed signal when the input data is set at a low level, to output a ground level voltage from the source output terminal as a low level shifted output data.