US5128760A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Television scan rate converter
Assignee: Texas Instruments Inc
•
Filing: 1990-07-30
•
Granted: 1992-07-07
•
Expires: 2010-07-30
Abstract
Abstract A single-instruction multiple-data processor (10) has an input layer especially designed for high data input and output rates. The processor (10) has a number of processing elements (20), each corresponding to incoming data samples. The processing elements (20) are interleaved so that a set of samples can be input in parallel. This configuration is especially useful for scan rate conversion, where the data output rate may not necessarily be the same as the data input rate.
Inventors
- 👤 Gerard Chauvel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:26
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; G; G06; G06T; G06T1/00; G06T1/20; H04; H04N; H04N7/00; H04N7/01; H04N7/0117; H04N7/012; H04N7/0127; H04N7/0132; H04N5/00; H04N5/14
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
253 words
A digital processing system, used in a television receiver, for converting an incoming television signal having certain scan characteristics to a display signal having different scan characteristics, comprising: a pair of luminance field memories, one for odd fields and one for even fields, for storing data samples of said incoming signal; a pair of chrominance field memories, one for odd fields and one for even fields, for storing data samples of said incoming signal; a pair of luminance single-instruction multiple-data processors for implementing a vertical filter process for changing the number of lines per field of said incoming signal, wherein one of said processors is in communication with said luminance field memory containing odd fields and operates on samples of said odd fields and wherein another one of said processors is in communication with said luminance field memory containing even fields and operates on samples of said even fields; a pair of chrominance single-instruction multiple-data processors for implementing a vertical filter process for changing the number of lines per field of said incoming signal, wherein one of said processors is in communication with said chrominance field memory containing odd fields and operates on samples of said odd fields and wherein another one of said processors is in communication with said chrominance field memory containing even fields and operates on samples of said even fields; an instruction generator associated with each of said processors for providing instructions to said processors; and a processor control unit for providing control and timing signals to said processors.
Claim 2
Dependent Claim
253 words
A digital processing system, used in a television receiver, for converting an incoming television signal having certain scan characteristics to a display signal having different scan characteristics, comprising: a pair of luminance field memories, one for odd fields and one for even fields, for storing data samples of said incoming signal; a pair of chrominance field memories, one for odd fields and one for even fields, for storing data samples of said incoming signal; a pair of luminance single-instruction multiple-data processors for implementing a vertical filter process for changing the number of lines per field of said incoming signal, wherein one of said processors is in communication with said luminance field memory containing odd fields and operates on samples of said odd fields and wherein another one of said processors is in communication with said luminance field memory containing even fields and operates on samples of said even fields; a pair of chrominance single-instruction multiple-data processors for implementing a vertical filter process for changing the number of lines per field of said incoming signal, wherein one of said processors is in communication with said chrominance field memory containing odd fields and operates on samples of said odd fields and wherein another one of said processors is in communication with said chrominance field memory containing even fields and operates on samples of said even fields; an instruction generator associated with each of said processors for providing instructions to said processors; and a processor control unit for providing control and timing signals to said processors.
Claim 3
Dependent Claim
42 words
The processing system of claim 1, and further comprising a luminance motion processor and a chrominance motion processor for implementing a filter function that changes the number of lines per field when said incoming signal indicates motion in the transmitted television picture.
Claim 4
Dependent Claim
25 words
The processing system of claim 2, and further comprising a switch for controlling the output of said processors, depending on an incoming motion detection signal.
Claim 5
Dependent Claim
57 words
The processing system of claim 1, wherein each of said field memories are comprised of a number of channels, said number of channels being determined by a preselected ratio of input data rate to output data rate, and further comprising an input control circuit associated with each of said processors for accepting parallel input from said channels.
Claim 6
Dependent Claim
45 words
The processing system of claim 4, wherein said input control circuit is comprised of a data selector circuit for directing data to virtual blocks of each of said processors and commutator cells for writing data in each block to adjacent processing elements of said processors.
Claim 7
Dependent Claim
307 words
A television receiving system for receiving an incoming video signal and converting its scan characteristics, comprising: color separation and analog to digital units for converting said incoming signal to data samples representing a digitized luminance signal and a digitized chrominance signal; a pair of luminance field memories, one for odd fields and one for even fields, for storing data samples of said incoming signal; a pair of chrominance field memories, one for odd fields and one for even fields, for storing data samples of said incoming signal; a pair of luminance single-instruction multiple-data processors for implementing a vertical filter process for changing the number of lines per field of said incoming signal, wherein one of said processors is in communication with said luminance field memory containing odd fields and operates on samples of said odd fields and wherein another one of said processors is in communication with said luminance field memory containing even fields and operates on samples of said even fields; a pair of chrominance single-instruction multiple-data processors for implementing a vertical filter process for changing the number of lines per field of said incoming signal, wherein one of said processors is in communication with said chrominance field memory containing odd fields and operates on samples of said odd fields and wherein another one of said processors is in communication with said chrominance field memory containing even fields and operates on samples of said even fields; an instruction generator associated with each of said processors for providing instructions to said processors; and a processor control unit for providing control and timing signals to said processors; a digital to analog unit for converting said data samples to an analog signal for display; a display unit in communication with said digital to analog unit for generating a picture signal for display; and a display for displaying said picture.
Claim 8
Dependent Claim
307 words
A television receiving system for receiving an incoming video signal and converting its scan characteristics, comprising: color separation and analog to digital units for converting said incoming signal to data samples representing a digitized luminance signal and a digitized chrominance signal; a pair of luminance field memories, one for odd fields and one for even fields, for storing data samples of said incoming signal; a pair of chrominance field memories, one for odd fields and one for even fields, for storing data samples of said incoming signal; a pair of luminance single-instruction multiple-data processors for implementing a vertical filter process for changing the number of lines per field of said incoming signal, wherein one of said processors is in communication with said luminance field memory containing odd fields and operates on samples of said odd fields and wherein another one of said processors is in communication with said luminance field memory containing even fields and operates on samples of said even fields; a pair of chrominance single-instruction multiple-data processors for implementing a vertical filter process for changing the number of lines per field of said incoming signal, wherein one of said processors is in communication with said chrominance field memory containing odd fields and operates on samples of said odd fields and wherein another one of said processors is in communication with said chrominance field memory containing even fields and operates on samples of said even fields; an instruction generator associated with each of said processors for providing instructions to said processors; and a processor control unit for providing control and timing signals to said processors; a digital to analog unit for converting said data samples to an analog signal for display; a display unit in communication with said digital to analog unit for generating a picture signal for display; and a display for displaying said picture.
Claim 9
Dependent Claim
43 words
The television receiving system of claim 6, and further comprising a luminance motion processor and a chrominance motion processor for implementing a filter function that changes the number of lines per field when said incoming signal indicates motion in the transmitted television picture.
Claim 10
Dependent Claim
26 words
The television receiving system of claim 7, and further comprising a switch for controlling the output of said processors, depending on an incoming motion detection signal.
Claim 11
Dependent Claim
58 words
The television receiving system of claim 6, wherein each of said field memories are comprised of a number of channels, said number of channels being determined by a preselected ratio of input data rate to output data rate, and further comprising an input control circuit associated with each of said processors for accepting parallel input from said channels.
Claim 12
Dependent Claim
46 words
The television receiving system of claim 9, wherein said input control circuit is comprised of a data selector circuit for directing data to virtual blocks of each of said processors and commutator cells for writing data in each block to adjacent processing elements of said processors.
Claim 13
Independent Claim
139 words
A method of using a single-instruction multiple data processor to convert an incoming television signal having certain scanning characteristics to a display signal having different scanning characteristics, comprising the steps of: storing data samples representing said incoming signal in memory, said memory separate from said processor; reading a set of said data samples in sequential order from said memory in a single time interval, wherein the number, n, of said data samples in said set is determined by a preselected data input rate to said processor; loading said n data samples to an input register of said processor during said time interval, wherein said input register is controlled so that said sequential order is maintained; communicating said data samples to a computational layer of said processor, while retaining said sequential order; and processing said data samples, using said processor.
Claim 14
Independent Claim
139 words
A method of using a single-instruction multiple data processor to convert an incoming television signal having certain scanning characteristics to a display signal having different scanning characteristics, comprising the steps of: storing data samples representing said incoming signal in memory, said memory separate from said processor; reading a set of said data samples in sequential order from said memory in a single time interval, wherein the number, n, of said data samples in said set is determined by a preselected data input rate to said processor; loading said n data samples to an input register of said processor during said time interval, wherein said input register is controlled so that said sequential order is maintained; communicating said data samples to a computational layer of said processor, while retaining said sequential order; and processing said data samples, using said processor.
Claim 15
Dependent Claim
26 words
The method of claim 11, wherein said processing step includes changing the number of lines per field of said incoming signal using a vertical filter function.
Claim 16
Dependent Claim
28 words
The method of claim 12, wherein said filter function is implemented with said single-instruction multiple data processor, using local memories of processing elements to store incoming data line-by-line.
Claim 17
Dependent Claim
24 words
The method of claim 13 and further comprising the step of using a global rotation process to supply said processing elements with incoming data.
Claim 18
Dependent Claim
26 words
The method of claim 12, and further comprising the step of determining whether there is motion in said incoming data and determining said filter function accordingly.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |