US4939575A
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US
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Fault-tolerant serial video processor device
Assignee: Texas Instruments Inc
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Filing: 1989-09-05
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Granted: 1990-07-03
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Expires: 2009-09-05
Abstract
Abstract A system for real-time digital processing of a video signal is disclosed, using a large number of one-bit serial processor elements, each operating on one pixel or a horizontal scan. The video signal is converted to digital by an A-to-D converter, and stored in a set of input registers, one register for each processor element. All of these input registers are loaded during a horizontal scan, as the input registers are addressed in sequence by a commutator. Each processor element includes a one-bit binary adder, a set of one-bit registers, and two wide data memories of a size to store data from several scans. The processor elements are all controlled in common by a sequencer, a state machine or a processor. The processed video data is transferred to an output register for each processor element, from which it is converted to a video signal by a D-to-A converter. A frame memory may be used to save a processed frame for use in convolving the next frame; the input of the frame memory is taken at the output registers, and the frame memory output is applied to the input registers. The number of processor elements of the linear array exceeds the number needed for the pixels of a horizontal scan, and laser-fused by-pass connections are included for by-passing processor elements which testing shows to be faulty.
Inventors
- 👤 Jimmie D. Childers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1666; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842; G06F15/80; G06F15/8007; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
368 words
A fault-tolerant, serial video device system for real-time processing of raster-scanned video, comprising: an input for receiving digitized, multi-bit video data; a set of N serial video processors, each one of said set of N video processors having: an input register connected to receive said multi-bit video data from said input; an output register connected to transfer multi-bit processed data from the video processor; first and second random-access memories each having data inputs and outputs connected to said input and output registers and each having an address input; a serial ALU having a plurality of one-bit registers and means to connect inputs and outputs of each said registers to data input and outputs of said first and second random-access memories, cross-connect means connecting inputs and outputs of the serial ALU to the serial ALU of adjacent video processors on the left and right; control inputs in common with all of said video processors receiving control and address sets of bits to select operation of the sense ALU and addressing of said first and second random-access memories to thereby perform one-bit serial arithmetic/logic operations in each of the set of N video processors for each set of control and address bits; commutator means having N stages addressing the input registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to load said multi-bit video data from said input into said input registers; and commutator means having N stages also addressing the output registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to transfer processed multi-bit video data to an output; control means having a multi-bit parallel output connected in common to said control inputs of all of said serial video processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said multi-bit video data, wherein each of said set of N serial video processors and said commutator means include by-pass means whereby selected ones of said serial video processors are omitted from operation of the device, the number N exceeding the number of processors needed for one line of said scan.
Claim 2
Dependent Claim
368 words
A fault-tolerant, serial video device system for real-time processing of raster-scanned video, comprising: an input for receiving digitized, multi-bit video data; a set of N serial video processors, each one of said set of N video processors having: an input register connected to receive said multi-bit video data from said input; an output register connected to transfer multi-bit processed data from the video processor; first and second random-access memories each having data inputs and outputs connected to said input and output registers and each having an address input; a serial ALU having a plurality of one-bit registers and means to connect inputs and outputs of each said registers to data input and outputs of said first and second random-access memories, cross-connect means connecting inputs and outputs of the serial ALU to the serial ALU of adjacent video processors on the left and right; control inputs in common with all of said video processors receiving control and address sets of bits to select operation of the sense ALU and addressing of said first and second random-access memories to thereby perform one-bit serial arithmetic/logic operations in each of the set of N video processors for each set of control and address bits; commutator means having N stages addressing the input registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to load said multi-bit video data from said input into said input registers; and commutator means having N stages also addressing the output registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to transfer processed multi-bit video data to an output; control means having a multi-bit parallel output connected in common to said control inputs of all of said serial video processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said multi-bit video data, wherein each of said set of N serial video processors and said commutator means include by-pass means whereby selected ones of said serial video processors are omitted from operation of the device, the number N exceeding the number of processors needed for one line of said scan.
Claim 3
Dependent Claim
34 words
A device according to claim 1 wherein an analog system input is connected to said input through an analog-to-digital converter, and said output is connected to an analog system output through a digital-to-analog converter.
Claim 4
Dependent Claim
44 words
A device according to claim 2 wherein said analog system input is sampled at a rate which is related to a multiple of the horizontal scan rate of said raster scan, said multiple being at least equal to the number of serial video processors.
Claim 5
Dependent Claim
31 words
A device according to claim 3 wherein said number N of said set of N serial video processors exceeds the number of pixels in a horizontal scan of said raster scan.
Claim 6
Dependent Claim
25 words
A system according to claim 1 wherein each of said first and second memories comprise a dynamic random access memory having a differential sense amplifier.
Claim 7
Dependent Claim
47 words
A system according to claim 1 wherein said input register of each video processor includes a first set of bits connected to receive said multi-bit video data in parallel from said input and a second set of bits connected in parallel to outputs of a frame memory.
Claim 8
Dependent Claim
55 words
A system according to claim 6 wherein said output register of each video processor includes a first set of bits connected to transfer in parallel said multi-bit processed data from said video processor to said output and a second set of bits connected to transfer processed data in parallel to inputs of said frame memory.
Claim 9
Dependent Claim
63 words
A system according to claim 7 wherein the number N of said set of N serial video processors is greater than the number of pixels in a horizontal scan of said raster scan, and there is a delay of at least one of said horizontal scans between input of video data to said input and the output of processed data at said output.
Claim 10
Dependent Claim
21 words
A system according to claim 8 wherein said frame memory stores processed video data for one frame of said raster scan.
Claim 11
Dependent Claim
32 words
A system according to claim 1 wherein each of said first and second random-access memories has a number of bits many times the number of bits in said input and output registers.
Claim 12
Dependent Claim
354 words
A serial processor system for high-speed processing, containing fault-tolerant processor elements, comprising; an input for receiving digitized, multi-bit signal data; a set of N serial processors in a linear array, each one of said set of N serial processors having: an input register connected to receive said multi-bit signal data from said input; an output register connected to transfer multi-bit processed data from the serial processor; random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input; a serial ALU element having a plurality of one-bit registers and connector means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means, cross connect means for connecting inputs and outputs of the ALU element to the serial ALU element of adjacent serial processors on the left and right; control inputs in common with all of said set of N serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations simultaneously in all of said sets of N serial processors for each separate set of control and address bits; first commutator means addressing the input registers of said set of N serial processors in a repeating sequence correlated with said signal data to load said multi-bit signal data from said input into said input registers; and second commutator means addressing the output registers of said set of N serial processors in a repeating sequence to transfer processed multi-bit data to an output; control means having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said serial processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said multi-bit signal data, wherein each one of said set of N serial processors and each one of said first and second commutor means has by-pass means whereby selected ones of said serial video processors are omitted from operation of the device.
Claim 13
Dependent Claim
354 words
A serial processor system for high-speed processing, containing fault-tolerant processor elements, comprising; an input for receiving digitized, multi-bit signal data; a set of N serial processors in a linear array, each one of said set of N serial processors having: an input register connected to receive said multi-bit signal data from said input; an output register connected to transfer multi-bit processed data from the serial processor; random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input; a serial ALU element having a plurality of one-bit registers and connector means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means, cross connect means for connecting inputs and outputs of the ALU element to the serial ALU element of adjacent serial processors on the left and right; control inputs in common with all of said set of N serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations simultaneously in all of said sets of N serial processors for each separate set of control and address bits; first commutator means addressing the input registers of said set of N serial processors in a repeating sequence correlated with said signal data to load said multi-bit signal data from said input into said input registers; and second commutator means addressing the output registers of said set of N serial processors in a repeating sequence to transfer processed multi-bit data to an output; control means having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said serial processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said multi-bit signal data, wherein each one of said set of N serial processors and each one of said first and second commutor means has by-pass means whereby selected ones of said serial video processors are omitted from operation of the device.
Claim 14
Dependent Claim
40 words
A system according to claim 11 wherein said random-access memory means includes first and second memories comprising dynamic random-access memory having one differential sense amplifier for each one of the first and second memories for each of the serial processors.
Claim 15
Dependent Claim
43 words
A system according to claim 11 wherein said input register of each serial processor includes a first set of bits connected to receive said multi-bit signal data from said input and a second set of bits connected to outputs of an auxiliary memory.
Claim 16
Dependent Claim
28 words
A system according to claim 11 wherein said random-access memory means has a number of bits many times the number of bits in said input and output registers.
Claim 17
Dependent Claim
338 words
A fault-tolerant, serial video device system for real-time processing of raster-scanned video, comprising: an input receiving a serial video signal: a set of N processors, each one of said set of N processors having: an input register connected to receive parts of said video signal from said input; an output register connected to transfer processed parts of said video signal from the processor; a serial ALU having a plurality of registers and multiplex leads to operate on said parts of said video signal in said input registers and place the same in said output registers; cross-connect means connecting inputs and outputs of the serial ALU to the serial ALU of adjacent processors on the left and right; and control inputs in common with all of said processors receiving control and address sets of bits to select operation of the serial ALU and addressing to thereby perform serial arithmetic/logic operations in each of the set of N processors for each set of control and address bits; a commutator circuit having N stages addressing the input registers of said set of N serial processors in a repeating sequence correlated with a raster scan to load said parts of said serial video signal circuit from said input into said input registers; and a commutator circuit having N stages also addressing the output registers of said set of N serial processors in a repeating sequence correlated with a raster scan to transfer said processed parts of said serial video signal to an output and a control circuit having a multi-bit parallel output connected in common to said control inputs of all of said processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said parts of said serial video signal, each of said set of N processors and said commutator circuits including by-pass circuits that omit selected ones of said processors from operation of the system, the number N exceeding the number of processors needed for one line of said scan.
Claim 18
Dependent Claim
338 words
A fault-tolerant, serial video device system for real-time processing of raster-scanned video, comprising: an input receiving a serial video signal: a set of N processors, each one of said set of N processors having: an input register connected to receive parts of said video signal from said input; an output register connected to transfer processed parts of said video signal from the processor; a serial ALU having a plurality of registers and multiplex leads to operate on said parts of said video signal in said input registers and place the same in said output registers; cross-connect means connecting inputs and outputs of the serial ALU to the serial ALU of adjacent processors on the left and right; and control inputs in common with all of said processors receiving control and address sets of bits to select operation of the serial ALU and addressing to thereby perform serial arithmetic/logic operations in each of the set of N processors for each set of control and address bits; a commutator circuit having N stages addressing the input registers of said set of N serial processors in a repeating sequence correlated with a raster scan to load said parts of said serial video signal circuit from said input into said input registers; and a commutator circuit having N stages also addressing the output registers of said set of N serial processors in a repeating sequence correlated with a raster scan to transfer said processed parts of said serial video signal to an output and a control circuit having a multi-bit parallel output connected in common to said control inputs of all of said processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said parts of said serial video signal, each of said set of N processors and said commutator circuits including by-pass circuits that omit selected ones of said processors from operation of the system, the number N exceeding the number of processors needed for one line of said scan.
Claim 19
Dependent Claim
32 words
A system according to claim 15 wherein an analog system input connects to said input through an analog-to-digital converter, and said output connects to an analog system output through a digital-to-analog converter.
Claim 20
Dependent Claim
42 words
A system according to claim 16 wherein said analog system input is sampled at a rate which is related to a multiple of the horizontal scan rate of said raster scan, said multiple being at least equal to the number of processors.
Claim 21
Dependent Claim
29 words
A system according to claim 17 wherein said number N of said set of N processors exceeds the number of pixels in a horizontal scan of said raster scan.
Claim 22
Dependent Claim
49 words
A system according to claim 15 wherein said input register of each processor includes a first set of bits connected to receive said parts of said serial video signal in parallel from said input and a second set of bits connected in parallel to outputs of a frame memory.
Claim 23
Dependent Claim
61 words
A system according to claim 19 wherein said output register of each processor includes a first set of bits connected to transfer in parallel said parts of said serial video signal from said processor to said output and a second set of bits connected to transfer processed parts of said serial video signal in parallel to inputs of said frame memory.
Claim 24
Dependent Claim
72 words
A system according to claim 20 wherein the nubmer N of said set of N processors is greater than the number of pixels in a horizontal scan of said raster scan, and there is a delay of at least one of said horizontal scans between input of said parts of said serial video signal to said input and the output of said processed parts of said serial video signal at said output.
Claim 25
Dependent Claim
24 words
A system according to claim 21 wherein said frame memory stores processed parts of said video signal for one frame of said raster scan.
Claim 26
Dependent Claim
323 words
A serial processor system for high-speed processing, containing fault-tolerant processor elements, comprising: an input for receiveing serial signal data: a set of N processors in a linear array, each one of said set of N processors having: an input register connected to receive a part of said serial signal data from said input; an output register connected to transfer processed data from the processor; a serial ALU element having a plurality of registers and connector means to connect inputs and outputs of each said registers to data inputs and outputs of said input and output registers; cross connect means for connecting inputs and outputs of the ALU element to the serial ALU element of adjacent processors on the left and right; control inputs in common with all of said set of N processors receiving sets of control and address bits to select operation of the connector means and addressing of said input and output registers to thereby perform arithmetic/logic operations simultaneously in all of said sets of N processors for each separate set of control and address bits; a first commutator circuit addressing the input registers of said set of N processors in a repeating sequence correlated with said signal data to load said serial signal data from said input into said input registers; and a second cummutator circuit addressing the output registers of said set of N processors in a repeating sequence to transfer processed signal data to an output; and a control circuit having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said serial signal data, each one of said set of N processors and each one of said first and second commutator circuits has a by-pass circuit that omit selected ones of said processors from operation of the system.
Claim 27
Dependent Claim
323 words
A serial processor system for high-speed processing, containing fault-tolerant processor elements, comprising: an input for receiveing serial signal data: a set of N processors in a linear array, each one of said set of N processors having: an input register connected to receive a part of said serial signal data from said input; an output register connected to transfer processed data from the processor; a serial ALU element having a plurality of registers and connector means to connect inputs and outputs of each said registers to data inputs and outputs of said input and output registers; cross connect means for connecting inputs and outputs of the ALU element to the serial ALU element of adjacent processors on the left and right; control inputs in common with all of said set of N processors receiving sets of control and address bits to select operation of the connector means and addressing of said input and output registers to thereby perform arithmetic/logic operations simultaneously in all of said sets of N processors for each separate set of control and address bits; a first commutator circuit addressing the input registers of said set of N processors in a repeating sequence correlated with said signal data to load said serial signal data from said input into said input registers; and a second cummutator circuit addressing the output registers of said set of N processors in a repeating sequence to transfer processed signal data to an output; and a control circuit having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said processors to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said serial signal data, each one of said set of N processors and each one of said first and second commutator circuits has a by-pass circuit that omit selected ones of said processors from operation of the system.
Claim 28
Dependent Claim
41 words
A system according to claim 23 wherein said input register of each processor includes a first set of bits connected to receive said signal data from said input and a second set of bits connected to outputs of an auxiliary memory.
Claim 29
Dependent Claim
189 words
A serial video device for real-time processing of raster-scanned video, comprising: an input for receiving digitized, multi-bit video data; a set of N serial video processors, each one of said set of N video processors having: an input register connected to receive said multi-bit video data from said input; an output register connected to transfer multi-bit processed data from the video processor; first and second random-access memories each having data inputs and outputs connected to said input and output registers and each having an address input; a serial arithmetic logic unit having a plurality of one-bit registers and means to connect inputs and outputs of each said registers to data inputs and outputs of said first and second random-access memories; control inputs in common with all of said video processors receiving control and address sets of bits to select operation of the serial arithmetic logic unit and addressing of said first and second random-access memories to thereby perform one-bit serial arithmetic/logic operations in each of the set of N video processors for each set of control and address bits; and an output connected to receive said multi-bit processed data.
Claim 30
Dependent Claim
189 words
A serial video device for real-time processing of raster-scanned video, comprising: an input for receiving digitized, multi-bit video data; a set of N serial video processors, each one of said set of N video processors having: an input register connected to receive said multi-bit video data from said input; an output register connected to transfer multi-bit processed data from the video processor; first and second random-access memories each having data inputs and outputs connected to said input and output registers and each having an address input; a serial arithmetic logic unit having a plurality of one-bit registers and means to connect inputs and outputs of each said registers to data inputs and outputs of said first and second random-access memories; control inputs in common with all of said video processors receiving control and address sets of bits to select operation of the serial arithmetic logic unit and addressing of said first and second random-access memories to thereby perform one-bit serial arithmetic/logic operations in each of the set of N video processors for each set of control and address bits; and an output connected to receive said multi-bit processed data.
Claim 31
Dependent Claim
46 words
The serial video device of claim 25, wherein each one of said set of N video processors further having: cross-connect means connecting inputs and outputs of the serial arithmetic logic unit to the serial arithmetic logic unit of adjacent video processors on the left and right.
Claim 32
Dependent Claim
87 words
The serial video device of claim 25, further comprising: first commutator means having N stages addressing the input registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to load said multi-bit video data from said input into said input registers; and second commutator means having N stages also addressing the output registers of said set of N serial video processors in a repeating sequence correlated with a raster scan to transfer processed multi-bit video data to said output.
Claim 33
Dependent Claim
54 words
The serial video device of claim 25, further comprising: control means having a multi-bit parallel output connected to common to said control inputs of all of said serial video processors to apply sequences of sets of control and address bits to said control inputs to result in real-time processing of said multi-bit video data.
Claim 34
Dependent Claim
59 words
The serial video device of claim 27, wherein each of said set of N serial video processors, and said first and second commutator means further comprise: means by-pass means whereby selected ones of said serial video processors are omitted from operation of the device, the number N exceeding the number of processors needed for one line of said scan.
Claim 35
Dependent Claim
191 words
A serial processor for high-speed processing, containing fault-toleran processor elements, comprising: an input for receiving digitized, multi-bit signal data; a set of N serial processors in a linear array, each one of said set of N serial processors having: an input register connected to receive said multi-bit signal data from said input; an output register connected to transfer multi-bit processed data from the serial processor; random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input; a serial arithmetic logic unit element having a plurality of one-bit registers and connector means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means; control inputs in common with all of said set of N serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations simultaneously in all of said sets of N serial processors for each separate set of control and address bits; and an output connected to receive said multi-bit processed data.
Claim 36
Dependent Claim
191 words
A serial processor for high-speed processing, containing fault-toleran processor elements, comprising: an input for receiving digitized, multi-bit signal data; a set of N serial processors in a linear array, each one of said set of N serial processors having: an input register connected to receive said multi-bit signal data from said input; an output register connected to transfer multi-bit processed data from the serial processor; random-access memory means having data inputs and outputs connected to said input and output registers and having at least one address input; a serial arithmetic logic unit element having a plurality of one-bit registers and connector means to connect inputs and outputs of each said registers to data inputs and outputs of said random-access memory means; control inputs in common with all of said set of N serial processors receiving sets of control and address bits to select operation of the multiplexer means and addressing of said random-access memory means to thereby perform one-bit serial arithmetic/logic operations simultaneously in all of said sets of N serial processors for each separate set of control and address bits; and an output connected to receive said multi-bit processed data.
Claim 37
Dependent Claim
71 words
The serial processor of claim 30, further comprising: first commutator means addressing the input registers of said set of N serial processors in a repeating sequence correlated with said signal data to load said multi-bit signal data from said input into said input registers; and second commutator means addressing the output registers of said set of N serial processors in a repeating sequence to transfer processed multi-bit data to said output.
Claim 38
Dependent Claim
55 words
The serial processor or claim 30, further comprising: control means having a multi-bit parallel output connected in common to said control inputs and address inputs for all of said serial processor to apply sequences of sets of control and address bits to said control inputs to result in high-speed processing of said multi-bit signal data.
Claim 39
Dependent Claim
45 words
The serial processor of claim 30, wherein each of said set of N processors further comprise: cross-connect means for connecting inputs and outputs of the arithmetic logic unit element to the serial arithmetic logic unit element of adjacent serial processors on the left and right.
Claim 40
Dependent Claim
46 words
The serial processor of claim 31, further comprising: wherein each one of said set of N serial processors and each one of said first and second commutator means has by-pass means whereby selected ones of said serial video processors re omitted from operation of the device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-02 | 1994-01-01 | 1994-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-02 | 1998-01-01 | 1998-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-02 | 2002-01-01 | 2002-07-03 | $7700.00 | Window Closed / Lapsed |