US4791677A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Image signal processor
Assignee: Panasonic Holdings Corp
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Filing: 1986-12-11
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Granted: 1988-12-13
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Expires: 2006-12-11
Abstract
Abstract An image signal processor which includes a local image register for receiving local image area data of m rows×n columns pixels, and a expansion use register of m row×l column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.
Inventors
- 👤 Toshiki Mori
- 👤 Haruyasu Yamada
- 👤 Kunitoshi Aono
- 👤 Masakatsu Maruyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:04
CPC Classifications
G; G06; G06T; G06T5/00; G06T5/20
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
72 words
An image signal processor comprising: a local image register for picking up local image area data of (m) rows×(n) columns; an expansion use register coupled to the output of said local image register for delaying the output of (m) rows×1 column; and a calculation unit coupled to said local image register for conducting calculation based upon said local image area data, said calculation unit having an input terminal which receives external data.
Claim 2
Dependent Claim
72 words
An image signal processor comprising: a local image register for picking up local image area data of (m) rows×(n) columns; an expansion use register coupled to the output of said local image register for delaying the output of (m) rows×1 column; and a calculation unit coupled to said local image register for conducting calculation based upon said local image area data, said calculation unit having an input terminal which receives external data.
Claim 3
Dependent Claim
17 words
The image signal processor of claim 1, wherein said local image register comprises (m×n) one-pixel shift registers.
Claim 4
Dependent Claim
15 words
The image signal processor of claim 2, wherein m is 3 and n is 3.
Claim 5
Dependent Claim
17 words
The image signal processor of claim 1, wherein said expansion use register comprises m one-pixel shift registers.
Claim 6
Dependent Claim
11 words
The image signal processor of claim 4, wherein m is 3.
Claim 7
Dependent Claim
175 words
An image signal processor comprising: at least first and second local image processors, each of said local image processors including a local image register, an expansion use register coupled to said local image register and a calculation unit coupled to said local image register, said first local image processor being designed to receive image data, which data is applied to said local image register, said second local image processor being designed to receive outputs of said expansion use register and calculation unit of said first local image processor, said output of the expansion use register being applied to said local image register of said second local image processor and said output of the calculation unit of the first local image processor being applied to the calculation unit of the second local image processor, whereby the output of the calculation unit of the first local image processor and the output of the local image register of the second local image processor are applied to and calculated by the calculation unit of the second local image processor.
Claim 8
Dependent Claim
175 words
An image signal processor comprising: at least first and second local image processors, each of said local image processors including a local image register, an expansion use register coupled to said local image register and a calculation unit coupled to said local image register, said first local image processor being designed to receive image data, which data is applied to said local image register, said second local image processor being designed to receive outputs of said expansion use register and calculation unit of said first local image processor, said output of the expansion use register being applied to said local image register of said second local image processor and said output of the calculation unit of the first local image processor being applied to the calculation unit of the second local image processor, whereby the output of the calculation unit of the first local image processor and the output of the local image register of the second local image processor are applied to and calculated by the calculation unit of the second local image processor.
Claim 9
Dependent Claim
147 words
An image signal processor comprising: a local image register for picking up local image area data of (m) rows×(n) columns; an expansion use register coupled to the output of said local image register for delaying the output of (m) rows×1 column; an arithmetic unit for conducting calculation of addition and subtraction based upon said local image area data; a clock control circuit coupled to said local image register and expansion use register for supplying clock signals thereto; a register coupled to said arithmetic unit for storing the output of said arthmetic unit; a selection circuit coupled to said arithmetic unit for selecting the input of said arithmetic unit; and an output control circuit coupled to said register which stores the output of said arithmetic unit for passing the output of the arithmetic unit therethrough for a predetermined period, said period being determined by said clock control circuit.
Claim 10
Dependent Claim
147 words
An image signal processor comprising: a local image register for picking up local image area data of (m) rows×(n) columns; an expansion use register coupled to the output of said local image register for delaying the output of (m) rows×1 column; an arithmetic unit for conducting calculation of addition and subtraction based upon said local image area data; a clock control circuit coupled to said local image register and expansion use register for supplying clock signals thereto; a register coupled to said arithmetic unit for storing the output of said arthmetic unit; a selection circuit coupled to said arithmetic unit for selecting the input of said arithmetic unit; and an output control circuit coupled to said register which stores the output of said arithmetic unit for passing the output of the arithmetic unit therethrough for a predetermined period, said period being determined by said clock control circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-12-13 | 1992-06-13 | 1992-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-13 | 1996-06-13 | 1996-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-13 | 2000-06-13 | 2000-12-13 | $7700.00 | Window Closed / Lapsed |