Patent US5128562A successfully refreshed from Google Patents.
US5128562A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory element with high metastability-immunity
Assignee: Philips North America LLC
•
Filing: 1990-12-19
•
Granted: 1992-07-07
•
Expires: 2010-12-19
Abstract
Abstract In a memory element comprising interconnected logic gates with field effect transistors metastable states are to be avoided. The device's immunity against staying in metastable states is considerably raised by coupling a supply terminal of each logic gate to a power supply voltage via a base-emitter path of a bipolar transistor that has its collector coupled to the logic gate's output.
Inventors
- 👤 Edward A. Burton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
160 words
An electronic circuit comprising: a first circuit supply node for receiving a first supply voltage; a second circuit supply node for receiving a second supply voltage; and two logic gates, each logic gate having: an input for receiving an input signal; an output coupled to the input of the other logic gate for providing an output signal; a first gate supply node coupled to the first circuit supply node; a second gate supply node coupled to the second circuit supply node; at least two field effect transistors arranged in series between the first and second gate supply nodes; and coupling means between the output and at least one of the first and second circuit supply nodes, each coupling means comprising: a collector-emitter path of a main bipolar transistor, the bipolar transistor having a base-emitter path arranged between a specified one of the first and second gate supply nodes and a specified one of the first and second circuit supply nodes.
Claim 2
Dependent Claim
160 words
An electronic circuit comprising: a first circuit supply node for receiving a first supply voltage; a second circuit supply node for receiving a second supply voltage; and two logic gates, each logic gate having: an input for receiving an input signal; an output coupled to the input of the other logic gate for providing an output signal; a first gate supply node coupled to the first circuit supply node; a second gate supply node coupled to the second circuit supply node; at least two field effect transistors arranged in series between the first and second gate supply nodes; and coupling means between the output and at least one of the first and second circuit supply nodes, each coupling means comprising: a collector-emitter path of a main bipolar transistor, the bipolar transistor having a base-emitter path arranged between a specified one of the first and second gate supply nodes and a specified one of the first and second circuit supply nodes.
Claim 3
Dependent Claim
39 words
The circuit of claim 1 wherein each logic gate further comprises: a current amplifier arranged between the specified gate supply node and a base of the main bipolar transistor for amplifying a base current for the main bipolar transistor.
Claim 4
Dependent Claim
57 words
The circuit of claim 2 wherein the current amplifier comprises: a further bipolar transistor with a base-emitter path arranged between the specified gate supply node and the base of the main bipolar transistor, and with a collector coupled to one of the following nodes: the other gate supply node; and a collector of the main bipolar transistor.
Claim 5
Dependent Claim
36 words
The circuit of claim 1 wherein each coupling means further comprises: pull-off means coupled between a base of the main bipolar transistor and the specified circuit supply node for selectively rendering the main bipolar transistor inactive.
Claim 6
Dependent Claim
49 words
The circuit of claim 4 wherein the pull-off means comprises at least one of the following: a main current path of a pull-off transistor coupled between the base of the main bipolar transistor and the specified circuit supply node and controlled by the output; a resistor; and a diode.
Claim 7
Dependent Claim
12 words
The circuit of claim 5 wherein the diode comprises a Schottky diode.
Claim 8
Dependent Claim
64 words
The circuit of claim 3 wherein each coupling means further comprises: first pull-off means coupled between the base of the main bipolar transistor and the specified circuit supply node for selectively rendering the main bipolar transistor inactive; and second pull-off means coupled between a base of the further bipolar transistor and the specified circuit supply node for selectively rendering the further bipolar transistor inactive.
Claim 9
Dependent Claim
133 words
The circuit of claim 7 wherein the first pull-off means comprises at least one of the following: a main current path of a first pull-off transistor coupled between the base of the main bipolar transistor and the specified circuit supply node and controlled by the output; a first resistor; and a first diode; and wherein the second pull-off means comprises at least one of the following: a main current path of a second pull-off transistor coupled between the base of the further bipolar transistor and the specified circuit supply node and controlled by the output; a main current path of a second pull-off transistor coupled between the base of the further bipolar transistor and the base of the main bipolar transistor and controlled by the output; a second resistor; and a second diode.
Claim 10
Dependent Claim
17 words
The circuit of claim 8 wherein each of the first and second diodes comprises a Schottky diode.
Claim 11
Dependent Claim
52 words
The circuit of claim 1 wherein the field effect transistors and the bipolar transistor of each logic gate have such sizes that at the output of each logic gate a signal transition from logic low to logic high lasts substantially as long as a signal transition from logic high to logic low.
Claim 12
Dependent Claim
57 words
The circuit of claim 1 wherein each one of the outputs is coupled to one of the first and second circuit supply nodes via a main current path of a respective bipolar discharge transistor that has a base coupled to that output via at least one respective field effect transistor switch controlled via a control signal input.
References Cited (Backward Citations)
US4719373A
Cited
US4983862A
Cited
US4845386A
Cited
US4929850A
Cited
US5047669A
Cited
US4963772A
Cited
US4999528A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |