System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor

Claim 2

A data processing system comprising: means for storing a sequence of instructions; means, connected to said storing means, for determining if said instruction sequence includes a branch instruction; means, connected to said storing means, responsive to said determining means for storing a sequence of branch target instructions in said storing means; means, connected to said storing means and said determining means, for dispatching instructions in said sequence to a first processor for execution and for dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, said dispatching means further including a second processor means for determining if said branch is to be taken, during a cycle with the dispatching of said instructions after said branch instruction; and means, connected to said dispatching means, for directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or for dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 3

A data processing system according to claim 1 wherein said means for storing a sequence of instructions includes means for fetching a plurality of instructions during a cycle.

Claim 4

A data processing system according to claim 2 wherein said dispatching means includes said means to dispatch a plurality of instructions during a cycle.

Claim 5

A data processing system according to claim 3 wherein said fetching means includes said means of storing said addresses of both a first instruction of said instructions in sequence after said branch instruction and a first instruction of said branch target instructions.

Claim 6

A data processing system according to claim 4 wherein said second processor means for executing said branch instruction includes means for determining a result of a previous instruction executed in said first processor.

Claim 7

A data processing system according to claim 5 wherein said storing means includes means for separately storing said branch target instructions from other instructions.

Claim 8

A data processing system comprising: means for fetching a plurality of instructions in sequence from a memory; a first buffer means, connected to said fetching means, for storing a portion of fetched instructions; means, connected to said first buffer means, for determining if a branch instruction is stored in said first buffer means; means, connected to said determining means, for fetching a sequence of branch target instructions in response to a branch instruction in said first buffer means; a second buffer means, connected to said fetching means, for storing a portion of said fetched branch target instructions; means, connected to said first buffer means, for dispatching sequential instructions located in sequence after said branch instruction form said first buffer means to a first processor for execution by said first processor on condition that a branch is not taken; a second processor, connected to said fetching means, for executing said branch instruction and determining if said branch is to be taken; means, connected to said second processor, for indicating to said first processor that said sequential instructions are to be executed if said branch is not taken; means, connected to said second buffer means, for dispatching instructions from said second buffer means to said first processor if said branch is taken; and means, connected to said second processor, for indicating to said first processor that said sequential instructions are not to be executed if said branch is taken.

Claim 9

A data processing system comprising: means for fetching a plurality of instructions in sequence from a memory; a first buffer means, connected to said fetching means, for storing a portion of fetched instructions; means, connected to said first buffer means, for determining if a branch instruction is stored in said first buffer means; means, connected to said determining means, for fetching a sequence of branch target instructions in response to a branch instruction in said first buffer means; a second buffer means, connected to said fetching means, for storing a portion of said fetched branch target instructions; means, connected to said first buffer means, for dispatching sequential instructions located in sequence after said branch instruction form said first buffer means to a first processor for execution by said first processor on condition that a branch is not taken; a second processor, connected to said fetching means, for executing said branch instruction and determining if said branch is to be taken; means, connected to said second processor, for indicating to said first processor that said sequential instructions are to be executed if said branch is not taken; means, connected to said second buffer means, for dispatching instructions from said second buffer means to said first processor if said branch is taken; and means, connected to said second processor, for indicating to said first processor that said sequential instructions are not to be executed if said branch is taken.

Claim 10

A data processing system according to claim 7 wherein said means for storing a sequence of instructions includes means for fetching a plurality of instructions during a cycle.

Claim 11

A data processing system according to claim 8 wherein said both dispatching means includes said means to dispatch a plurality of instructions during a cycle.

Claim 12

A data processing system according to claim 9 wherein said fetching means includes said means of storing said addresses of both a first instruction of said instructions in sequence after said branch instruction and a first instruction of said branch target instructions.

Claim 13

A data processing system according to claim 10 wherein said second processor includes means for determining a result of a previous instruction executed in said first processor.

Claim 14

A data processing system according to claim 11 wherein said storing means includes means for separately storing said branch target instructions from other instructions.

Claim 15

A data processing system according to claim 7 wherein said second processor includes means for storing a branch instruction dependent upon an unresolved condition, in a register until the unresolved condition is resolved and said means for dispatching instructions for execution on condition that a branch is not taken continues to dispatch said instructions until said condition is resolved.

Claim 16

A data processing system according to claim 13 wherein said second processor includes means for determining when said condition is resolved by determining when said first processor executing an instruction on which the branch instruction depends, stores a condition code to the means for executing said branch instruction and determining if said branch is to be taken.

Claim 17

A data processing system comprising: means for storing a sequence of instructions; means, connected to said storing means, for determining if said instruction sequence includes a conditional branch instruction dependent upon a result from a previous instruction in said sequence; means, connected to said storing means, responsive to said determining means for storing a sequence of branch target instructions in said storing means; means, connected to said storing means and said branch instruction including determining means, for dispatching instructions in said sequence to a first processor for execution and for dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, said dispatching means further including a second processor for determining if said branch is to be taken, during cycle with the dispatching of said instructions after said branch instruction; and means, connected to said dispatching means, for directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or for dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 18

A data processing system comprising: means for storing a sequence of instructions; means, connected to said storing means, for determining if said instruction sequence includes a conditional branch instruction dependent upon a result from a previous instruction in said sequence; means, connected to said storing means, responsive to said determining means for storing a sequence of branch target instructions in said storing means; means, connected to said storing means and said branch instruction including determining means, for dispatching instructions in said sequence to a first processor for execution and for dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, said dispatching means further including a second processor for determining if said branch is to be taken, during cycle with the dispatching of said instructions after said branch instruction; and means, connected to said dispatching means, for directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or for dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 19

A data processing system according to claim 15 wherein said means for storing a sequence of instructions includes means for fetching a plurality of instructions during a cycle.

Claim 20

A data processing system according to claim 16 wherein said dispatching means includes said means to dispatch a plurality of instructions during a cycle.

Claim 21

A data processing system according to claim 17 wherein said fetching means includes said means of storing said addresses of both a first instruction of said instructions in sequence after said branch instruction and a first instruction of said branch target instructions.

Claim 22

A data processing system according to claim 18 wherein said first processor includes means for setting a condition register with said result of said previous instruction execution in said sequence and said second processor includes means for reading said condition register.

Claim 23

A data processing system according to claim 19 wherein said storing means includes means for separately storing said branch target instructions from other instructions.

Claim 24

A data processing system comprising: means for storing a sequence of instructions; means, connected to said storing means, for determining if said instruction sequence includes a branch instruction; means, connected to said storing means, responsive to said determining means for storing a sequence of branch target instructions in said storing means while during a same cycle dispatching instructions in sequence to a first processor for execution and including means for dispatching instructions in sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken during a cycle before a determination of whether said branch will be taken; a second processor means, connected to said means responsive to said branch instruction including determining means, for determining if said branch is to be taken; and means, connected to said second processor means, for directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or for dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 25

A data processing system comprising: means for storing a sequence of instructions; means, connected to said storing means, for determining if said instruction sequence includes a branch instruction; means, connected to said storing means, responsive to said determining means for storing a sequence of branch target instructions in said storing means while during a same cycle dispatching instructions in sequence to a first processor for execution and including means for dispatching instructions in sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken during a cycle before a determination of whether said branch will be taken; a second processor means, connected to said means responsive to said branch instruction including determining means, for determining if said branch is to be taken; and means, connected to said second processor means, for directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or for dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 26

A data processing system according to claim 21 wherein said means for storing a sequence of instructions includes means for fetching a plurality of instructions during a cycle.

Claim 27

A data processing system according to claim 22 wherein said dispatching means includes said means to dispatch a plurality of instructions during a cycle.

Claim 28

A data processing system according to claim 23 wherein said fetching means includes said means of storing said addresses of both a first instruction of said instructions in sequence after said branch instruction and a first instruction of said branch target instructions.

Claim 29

A data processing system according to claim 24 wherein said second processor means includes means for determining a result of a previous instruction executed in said first processor.

Claim 30

A data processing system according to claim 25 wherein said storing means includes means for separately storing said branch target instructions from other instructions.

Claim 31

A pipelined data processing system comprising: means for fetching a sequence of instructions during a cycle; means, connected to said fetching means, for determining if said instruction sequence includes a branch instruction and in response to a determination of a branch instruction, for storing a sequence of branch target instructions in said storing means; means, connected to said fetching means, for dispatching a plurality of said fetched instructions in a cycle to a first processor for execution and for dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, where said instructions are dispatched during a cycle before a determination of whether said branch will be taken; a second processor for determining whether said branch will be taken; means, connected to said dispatching means, for decoding said dispatched instructions in a cycle; and means, connected to said decoding means and said second processor, for executing said decoded instructions in a cycle and including means for directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or for dispatching, fi said branch is taken, said branch target instructions to said first processor execution.

Claim 32

A pipelined data processing system comprising: means for fetching a sequence of instructions during a cycle; means, connected to said fetching means, for determining if said instruction sequence includes a branch instruction and in response to a determination of a branch instruction, for storing a sequence of branch target instructions in said storing means; means, connected to said fetching means, for dispatching a plurality of said fetched instructions in a cycle to a first processor for execution and for dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, where said instructions are dispatched during a cycle before a determination of whether said branch will be taken; a second processor for determining whether said branch will be taken; means, connected to said dispatching means, for decoding said dispatched instructions in a cycle; and means, connected to said decoding means and said second processor, for executing said decoded instructions in a cycle and including means for directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or for dispatching, fi said branch is taken, said branch target instructions to said first processor execution.

Claim 33

In a data processing system a method of processing comprising said steps of: storing a sequence of instructions; determining if said instruction sequence includes a branch instruction; storing a sequence of branch target instruction if said sequence of instructions includes a branch instruction; dispatching instructions in said sequence to a first processor for executing and dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, where said instructions are dispatched during a cycle before a determination whether said branch will be taken in a second processor; and directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 34

In a data processing system a method of processing comprising said steps of: storing a sequence of instructions; determining if said instruction sequence includes a branch instruction; storing a sequence of branch target instruction if said sequence of instructions includes a branch instruction; dispatching instructions in said sequence to a first processor for executing and dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, where said instructions are dispatched during a cycle before a determination whether said branch will be taken in a second processor; and directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 35

In a data processing system a method of processing comprising steps of: fetching a plurality of instructions in a sequence from a memory; storing a portion of fetched instructions; determining if a branch instruction is stored; fetching a sequence of branch target instructions in response to a branch instruction in said instruction sequence; storing a portion of said fetched branch target instructions; dispatching said first stored instructions to a first processor for execution by said first processor on condition that a branch is not taken; executing said branch instruction in a second processor and determining if said branch is to be taken; when said second processor determines that said branch is not taken, indicating by said second processor to said first processor that said dispatched first instructions are to be executed and executing said first stored instructions; when said second processor determines that said branch is to be taken dispatching said branch target instructions to said first processor and executing said branch target instructions; and indicating to said first processor that said conditional instructions are not to be executed if said branch is taken.

Claim 36

In a data processing system a method of processing comprising steps of: fetching a plurality of instructions in a sequence from a memory; storing a portion of fetched instructions; determining if a branch instruction is stored; fetching a sequence of branch target instructions in response to a branch instruction in said instruction sequence; storing a portion of said fetched branch target instructions; dispatching said first stored instructions to a first processor for execution by said first processor on condition that a branch is not taken; executing said branch instruction in a second processor and determining if said branch is to be taken; when said second processor determines that said branch is not taken, indicating by said second processor to said first processor that said dispatched first instructions are to be executed and executing said first stored instructions; when said second processor determines that said branch is to be taken dispatching said branch target instructions to said first processor and executing said branch target instructions; and indicating to said first processor that said conditional instructions are not to be executed if said branch is taken.

Claim 37

In a data processing system a method of processing comprising said steps of; storing a sequence of instructions; determining if said instruction sequence includes a conditional branch instruction dependent upon a result from a previous instruction in said sequence; storing a sequence of branch target instructions in said storing means if a conditional branch instruction is in said instruction sequence; dispatching instructions in said sequence to a first processor for execution and dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, where said instructions are dispatched during a cycle before a determination of whether said branch will be taken by a second processor; and directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 38

In a data processing system a method of processing comprising said steps of; storing a sequence of instructions; determining if said instruction sequence includes a conditional branch instruction dependent upon a result from a previous instruction in said sequence; storing a sequence of branch target instructions in said storing means if a conditional branch instruction is in said instruction sequence; dispatching instructions in said sequence to a first processor for execution and dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken, where said instructions are dispatched during a cycle before a determination of whether said branch will be taken by a second processor; and directing, if said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 39

In a data processing system a method of processing comprising said steps of: storing a sequence of instructions; determining if said instruction sequence includes a branch instruction; storing a sequence of branch target instructions if a branch instruction is in said instruction sequence while during a same cycle dispatching instructions in sequence to a first processor for execution and dispatching instructions in sequence after said branch instruction to said processor to be executed on condition that said branch is not taken during a cycle before a determination of whether said branch will be taken a said second processor; determining if said branch is to be taken a said second processor; and directing, fi said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 40

In a data processing system a method of processing comprising said steps of: storing a sequence of instructions; determining if said instruction sequence includes a branch instruction; storing a sequence of branch target instructions if a branch instruction is in said instruction sequence while during a same cycle dispatching instructions in sequence to a first processor for execution and dispatching instructions in sequence after said branch instruction to said processor to be executed on condition that said branch is not taken during a cycle before a determination of whether said branch will be taken a said second processor; determining if said branch is to be taken a said second processor; and directing, fi said branch is not taken, said first processor to execute said instructions in sequence after said branch instruction or dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 41

In a pipelined data processing system, a method of processing comprising the steps of; fetching a sequence of instructions during a cycle; determining if said instruction sequence includes a branch instruction and in response to a determination of a branch instruction, storing a sequence of branch target instructions; dispatching a plurality of said fetched instructions in a cycle to a first processor for execution and dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken during a cycle before a determination of whether said branch will be taken by a second processor; decoding said dispatched instructions in a cycle; and executing said decoded instructions in a cycle and including a step of directing, if said branch is not taken, said first processor to execute said instructions or dispatching, if said branch is taken, said branch target instructions to said first processor for execution.

Claim 42

In a pipelined data processing system, a method of processing comprising the steps of; fetching a sequence of instructions during a cycle; determining if said instruction sequence includes a branch instruction and in response to a determination of a branch instruction, storing a sequence of branch target instructions; dispatching a plurality of said fetched instructions in a cycle to a first processor for execution and dispatching instructions in said sequence after said branch instruction to said first processor to be executed on condition that said branch is not taken during a cycle before a determination of whether said branch will be taken by a second processor; decoding said dispatched instructions in a cycle; and executing said decoded instructions in a cycle and including a step of directing, if said branch is not taken, said first processor to execute said instructions or dispatching, if said branch is taken, said branch target instructions to said first processor for execution.