Patent US5126846A successfully refreshed from Google Patents.
US5126846A
Expired / Lapsed
US
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Non-linear amplifier and non-linear emphasis/deemphasis circuit using the same
Assignee: Toshiba Corp
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Filing: 1989-08-02
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Granted: 1992-06-30
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Expires: 2009-08-02
Abstract
Abstract A non-linear amplifier circuit comprises a low band eliminating filter for receiving an input signal from an input terminal, a logarithmic amplifier and an adder for adding the output signal of this logarithmic amplifier and the input signal with a predetermined polarity relationship to produce an output signal and sending this output signal to an output terminal. The logarithmic amplifier comprises an amplifier for receiving the output signal of the low band eliminating filter, a bidirectional logarithmic element and a resistor coupled in parallel thereto between the input and output terminals of the amplifier.
Inventors
- 👤 Kazuharu Niimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:07
CPC Classifications
H; H03; H03G; H03G9/00; H03G9/02; H03G9/025; H03G7/00; H03G7/002; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/92; H04N5/923
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
137 words
A non-linear amplifier circuit comprising: low band eliminating filter means for receiving an input signal and outputting an output signal obtained by removing a low frequency signal from said input signal; logarithmic amplifier means for receiving said output signal of said low band eliminating filter means and outputting an output signal, said logarithmic amplifier means including an amplifier having an input terminal and an output terminal, and a bidirectional logarithmic element and a resistor which are coupled in parallel between said input and output terminals of said amplifier; adder means for adding said output signal of said logarithmic amplifier means and said input signal with a predetermined polarity relationship and outputting an output signal; and a delay element provided in a path of said low band eliminating filter means, said logarithmic amplifier means and said adder means.
Claim 2
Dependent Claim
137 words
A non-linear amplifier circuit comprising: low band eliminating filter means for receiving an input signal and outputting an output signal obtained by removing a low frequency signal from said input signal; logarithmic amplifier means for receiving said output signal of said low band eliminating filter means and outputting an output signal, said logarithmic amplifier means including an amplifier having an input terminal and an output terminal, and a bidirectional logarithmic element and a resistor which are coupled in parallel between said input and output terminals of said amplifier; adder means for adding said output signal of said logarithmic amplifier means and said input signal with a predetermined polarity relationship and outputting an output signal; and a delay element provided in a path of said low band eliminating filter means, said logarithmic amplifier means and said adder means.
Claim 3
Dependent Claim
31 words
A non-linear amplifier circuit according to claim 1, wherein said adder means comprises an adder for outputting said output signal to said low band eliminating filter means and an output terminal.
Claim 4
Dependent Claim
25 words
A non-linear amplifier circuit according to claim 1, wherein said bidirectional logarithmic element comprises a plurality of diodes coupled in parallel in reverse bias directions.
Claim 5
Dependent Claim
36 words
A non-linear amplifier circuit according to claim 1, wherein said bidirectional logarithmic element comprises a plurality of transistors each having a collector and a base coupled together and having base-emitter paths coupled in mutually reverse directions.
Claim 6
Dependent Claim
31 words
A non-linear amplifier circuit according to claim 1, wherein said bidirectional logarithmic element comprises a plurality of transistors having base-emitter paths coupled in reverse directions and each having a base grounded.
Claim 7
Dependent Claim
33 words
A non-linear amplifier circuit according to claim 1, wherein said low band eliminating filter means comprises a filter for outputting said output signal thereof as a current signal to said logarithmic amplifier means.
Claim 8
Dependent Claim
33 words
A non-linear amplifier circuit according to claim 1, wherein said low band eliminating filter means comprises a filter for outputting said output signal thereof as a voltage signal to said logarithmic amplifier means.
Claim 9
Dependent Claim
117 words
A non-linear amplifier circuit comprising: a low band eliminating filter for receiving an input signal from an input terminal and for eliminating low frequency components from the input signal to output a first output signal; an emphasis circuit receiving the first output signal from said low band eliminating filter and outputting a second output signal; an adder for adding the second output signal from said emphasis circuit and the input signal with a predetermined polarity relationship and outputting a third output signal obtained by the addition to an output terminal; and at least one delay element provided in a path from said input terminal to said adder through said low band eliminating filter and said emphasis circuit.
Claim 10
Dependent Claim
117 words
A non-linear amplifier circuit comprising: a low band eliminating filter for receiving an input signal from an input terminal and for eliminating low frequency components from the input signal to output a first output signal; an emphasis circuit receiving the first output signal from said low band eliminating filter and outputting a second output signal; an adder for adding the second output signal from said emphasis circuit and the input signal with a predetermined polarity relationship and outputting a third output signal obtained by the addition to an output terminal; and at least one delay element provided in a path from said input terminal to said adder through said low band eliminating filter and said emphasis circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-30 | 1995-12-30 | 1996-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-30 | 1999-12-30 | 2000-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-30 | 2003-12-30 | 2004-06-30 | $7700.00 | Window Closed / Lapsed |