Patent US5126807A successfully refreshed from Google Patents.
US5126807A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertical MOS transistor and its production method
Assignee: Toshiba Corp
•
Filing: 1991-06-12
•
Granted: 1992-06-30
•
Expires: 2011-06-12
Abstract
Abstract A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.
Inventors
- 👤 Yoshiro Baba
- 👤 Shunichi Hiraki
- 👤 Akihiko Osawa
- 👤 Satoshi Yanagiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:48
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/40; H10D30/00; H10D30/01; H10D30/021; H10D30/025; H10D30/60; H10D30/611; H10D30/64; H10D30/66; H10D30/668; H10D64/00; H10D64/111; H10D64/117; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10D64/517; H10D64/518; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/016
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
158 words
A vertical MOS transistor, comprising: (a) a semiconductor substrate; (b) a first impurity region defined on the surface of said semiconductor substrate; (c) a second impurity region defined under said first impurity region, the conductivity type of said second impurity region being opposite to that of said first impurity region; (d) a trench engraved on the surface of said semiconductor substrate to cut through said first and second impurity regions deeper than at least a bottom of said second impurity region; (e) a first gate electrode disposed on a bottom of said trench with a first gate insulation film interposing between a wall of said trench and said first gate electrode; and (f) a second gate electrode disposed over said first gate electrode in said trench with a second gate insulation film interposing between the wall of said trench and said second gate electrode, (g) said first gate insulation film being thicker than said second gate insulation film.
Claim 2
Dependent Claim
158 words
A vertical MOS transistor, comprising: (a) a semiconductor substrate; (b) a first impurity region defined on the surface of said semiconductor substrate; (c) a second impurity region defined under said first impurity region, the conductivity type of said second impurity region being opposite to that of said first impurity region; (d) a trench engraved on the surface of said semiconductor substrate to cut through said first and second impurity regions deeper than at least a bottom of said second impurity region; (e) a first gate electrode disposed on a bottom of said trench with a first gate insulation film interposing between a wall of said trench and said first gate electrode; and (f) a second gate electrode disposed over said first gate electrode in said trench with a second gate insulation film interposing between the wall of said trench and said second gate electrode, (g) said first gate insulation film being thicker than said second gate insulation film.
Claim 3
Dependent Claim
15 words
The vertical MOS transistor according to claim 1, wherein said trench reaches said semiconductor substrate.
Claim 4
Dependent Claim
22 words
The vertical MOS transistor according to claim 1, wherein a capacitance insulation film is formed between said first and second gate electrodes.
Claim 5
Dependent Claim
21 words
The vertical MOS transistor according to claim 1, wherein said first and second gate electrodes are electrically connected to each other.
Claim 6
Dependent Claim
172 words
A vertical MOS transistor, comprising: (a) a semiconductor substrate; (b) a first impurity region defined on the surface of said semiconductor substrate; (c) a second impurity region defined under said first impurity region, the conductivity type of said second impurity region being opposite to that of said first impurity region; (d) a trench engraved on the surface of said semiconductor substrate to cut through said first and second impurity regions deeper than at least the bottom of said second impurity region; (e) a floating gate electrode disposed on the bottom of said trench with a first gate insulation film interposing between a wall of said trench and said floating gate electrode; and (f) a main gate electrode disposed over said floating gate electrode with a capacitance insulation film interposing between said floating gate electrode and said main gate electrode and with a second gate insulation film interposing between said main electrode and said first and second impurity regions, (g) said first gate insulation film being thicker than said second gate insulation film.
Claim 7
Dependent Claim
172 words
A vertical MOS transistor, comprising: (a) a semiconductor substrate; (b) a first impurity region defined on the surface of said semiconductor substrate; (c) a second impurity region defined under said first impurity region, the conductivity type of said second impurity region being opposite to that of said first impurity region; (d) a trench engraved on the surface of said semiconductor substrate to cut through said first and second impurity regions deeper than at least the bottom of said second impurity region; (e) a floating gate electrode disposed on the bottom of said trench with a first gate insulation film interposing between a wall of said trench and said floating gate electrode; and (f) a main gate electrode disposed over said floating gate electrode with a capacitance insulation film interposing between said floating gate electrode and said main gate electrode and with a second gate insulation film interposing between said main electrode and said first and second impurity regions, (g) said first gate insulation film being thicker than said second gate insulation film.
Claim 8
Dependent Claim
15 words
The vertical MOS transistor according to claim 5, wherein said trench reaches said semiconductor substrate.
Claim 9
Dependent Claim
23 words
The vertical MOS transistor according to claim 5, wherein said floating gate electrode and main gate electrode are electrically connected to each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-30 | 1995-12-30 | 1996-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-30 | 1999-12-30 | 2000-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-30 | 2003-12-30 | 2004-06-30 | $7700.00 | Window Closed / Lapsed |