US5125094A
Expired / Lapsed
US
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Apparatus for using an ALU as a temporary storage for data during an otherwise idle cycle of the ALU
Assignee: Toshiba Corp
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Filing: 1989-09-08
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Granted: 1992-06-23
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Expires: 2009-09-08
Abstract
Abstract A data-processing device has a clock generator for generating pulse signals φ1 and φ2, an ALU capable of executing various arithmetic-logic operations during cycles corresponding to the pulse signals φ1 and φ2,and a control unit for generating a control signal which causes the ALU to execute an arithmetic-logic operation according to an instruction. This data-processing device further includes a transfer switch for causing the ALU to execute an arithmetic-logic operation, which is for generating output data equal to input data, during a cycle in which the ALU would otherwise be idle.
Inventors
- 👤 Yuriko Kyuma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:52
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3868
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
205 words
A data processing device performing a series of instructions, at least one of the instructions being a selected arithmetic-logic instruction specifying at least one arithmetic-logic operation and input data, said data processing device comprising: arithmetic-logic means for performing said at least one arithmetic-logic operation specified by the selected arithmetic-logic instruction in said series, said arithmetic-logic means performing said at least one arithmetic-logic operation during instruction cycles composed of at least one machine cycle; clock generating means, connected to said arithmetic-logic means, for generating a clock signal defining said machine cycles for said arithmetic-logic means, wherein a machine cycle during which said arithmetic-logic means performs no arithmetic-logic operation specified by said selected arithmetic-logic instruction is called an idle cycle; control means, connected to said clock generating means and said arithmetic-logic means, for sending said input data specified by said selected arithmetic-logic instruction to said arithmetic-logic means, and for causing, during an idle cycle, said arithmetic-logic means to produce output data identical to said input data so that said input data is temporarily stored in said arithmetic logic means; memory means for storing the series of instructions and said input data; and bus means for connecting said memory means to said arithmetic-logic means and said control means.
Claim 2
Dependent Claim
205 words
A data processing device performing a series of instructions, at least one of the instructions being a selected arithmetic-logic instruction specifying at least one arithmetic-logic operation and input data, said data processing device comprising: arithmetic-logic means for performing said at least one arithmetic-logic operation specified by the selected arithmetic-logic instruction in said series, said arithmetic-logic means performing said at least one arithmetic-logic operation during instruction cycles composed of at least one machine cycle; clock generating means, connected to said arithmetic-logic means, for generating a clock signal defining said machine cycles for said arithmetic-logic means, wherein a machine cycle during which said arithmetic-logic means performs no arithmetic-logic operation specified by said selected arithmetic-logic instruction is called an idle cycle; control means, connected to said clock generating means and said arithmetic-logic means, for sending said input data specified by said selected arithmetic-logic instruction to said arithmetic-logic means, and for causing, during an idle cycle, said arithmetic-logic means to produce output data identical to said input data so that said input data is temporarily stored in said arithmetic logic means; memory means for storing the series of instructions and said input data; and bus means for connecting said memory means to said arithmetic-logic means and said control means.
Claim 3
Dependent Claim
94 words
The data processing device of claim 1, wherein said selected arithmetic-logic instruction includes an operation code specifying said at least one arithmetic-logic operation, and wherein said control means includes: an instruction register for storing the operation code of said selected arithmetic-logic instruction; an instruction decoder connected to said instruction register for decoding the operation code stored in said instruction register and for producing an output signal according to the operation code; and a control circuit connected to said instruction decoder for controlling said arithmetic-logic means according to said output signal of said instruction decoder.
Claim 4
Dependent Claim
80 words
The data processing device of claim 2, wherein said arithmetic-logic means includes: an address counter; an arithmetic-logic unit, having inputs, and performing, during an idle cycle, a predetermined arithmetic-logic operation on index offset data received from said memory means at a first one of said inputs, responsive to said control circuit; and a data supply section for supplying predetermined data to a second one of said inputs of said arithmetic-logic unit, during said idle cycle, responsive to said control circuit.
Claim 5
Dependent Claim
28 words
The data processing device of claim 3, wherein said predetermined data is a plurality of Boolean zeroes, and wherein said predetermined logic-operations include addition, subtraction, and "OR" operations.
Claim 6
Dependent Claim
26 words
The data processing device of claim 3, wherein said predetermined data is a plurality of Boolean ones, and wherein said predetermined arithmetic-logic operations include an "AND"operation.
Claim 7
Dependent Claim
69 words
The data processing device of claim 3, wherein at least said selected arithmetic-logic instruction has a three word instruction format, said three words of said instruction format including a word having said index offset data, said three words being stored in succession in said memory means and wherein, responsive to said control circuit, said arithmetic-logic unit receives said index offset data from said memory means during said idle cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |