Organization for an integrated circuit calculator/controller

Claim 1

A structure for a microprocessor comprising: an arithmetic logic unit, said arithmetic logic unit comprising a plurality of logic elements and means for selectively configuring said logic elements into a plurality of distinct combinations; a plurality of data storage registers for containing data, said data storage registers being connected in parallel with said arithmetic logic unit by means of an input bus and an output bus; a plurality of memory means connected in parallel with said arithmetic logic unit and said data storage registers by means of said input bus and said output bus; program storage means, said program storage means containing a plurality of instructions; control means: program pointer means responsive to said control means for selectively addressing one of said plurality of instructions contained in said program storage means; instruction storage means for storing said selected instruction, said instruction storage means capable of communicating with said program pointer means for selectively loading said selected instruction into said program pointer means in response to a signal from said control means; auxiliary instruction storage means communicating with said program pointer means for storing said selected instruction contained in said program pointer means, said auxiliary instruction storage means capable of selectively loading said selected instruction into said program pointer means all in response to a signal from said control means; configuration control means connected to said instruction storage means for decoding a portion of said selected instruction contained in said instruction storage means to generate a configuration signal for selectively configuring said logic elements of said arithmetic logic unit; register select control means connected to said instruction storage means for decoding the remainder of said selected instruction contained in said instruction storage means to generate a register select signal for selectively actuating selected storage registers, said data contents of said selected storage registers being modified by selectively configured logic elements of said arithmetic logic unit; input/output means connected to said data storage registers for transferring data into and out of said selected data storage registers, respectively, in response to execution of an instruction contained in said instruction storage means; and data clocking means connected to said arithmetic logic unit, said control means, and said configuration control means for controllably sequencing the operation of said arithmetic logic unit, said control means, and said configuration control means.