Thin film transistor and active matrix assembly including same

Claim 2

A metal-oxide-semiconductor transistor comprising: a glass insulating substrate; a thin film of silicon selected from the group consisting of polycrystalline silicon and amorphous silicon including a channel region of less than 2500 Å thickness disposed on said substrate; a source region and a drain region in said thin film silicon and spaced apart by said channel region, said source region and drain region formed from a dopant material and having throughout its region a thickness greater than the thickness of said channel region; an insulating film disposed on the surface of said thin film contacting at least a portion of the surface of each of said source, drain and channel regions; a gate electrode disposed on said insulating film and between said source and drain regions; and means for connecting said spaced apart source and drain regions and said gate electrode to external circuitry.

Claim 3

The metal-oxide-semiconductor transistor of claim 1, wherein the silicon thin film is a polycrystalline silicon.

Claim 4

The metal-oxide-semiconductor transistor of claim 1, wherein the silicon thin film is intrinsic polycrystalline silicon.

Claim 5

The metal-oxide-semiconductor transistor of claim 1, wherein the insulating film is a silicon oxide film.

Claim 6

The metal-oxide-semiconductor transistor of claim 4, wherein the silicon oxide film is a thermally oxidized film of intrinsic polycrystalline silicon.

Claim 7

The metal-oxide-semiconductor transistor of claim 1, wherein said gate is formed of a material selected from a group consisting of polycrystalline silicon, metal silicofluoxide, or metal.

Claim 8

The metal-oxide-semiconductor transistor of claim 1, wherein the glass substrate is quartz glass.

Claim 9

An active matrix assembly for a liquid crystal display device comprising: a plurality of liquid crystal driving electrodes arranged in a matrix of columns and rows; a plurality of data lines and address lines arranged in columns and rows of said matrix and intersecting each other to form a plurality of cross-over points; and a plurality of thin film transistors and liquid crystal driving electrodes located at the cross-over points of said data lines and address lines, said transistors for electrically coupling the data lines and address lines to each driving electrode and formed on a glass substrate using a non-monocrystalline silicon thin film; and wherein the thin film has a source region, a drain region and a channel region, formed in said thin film, said source region and drain region being spaced apart by said channel region, said channel region having a thickness of less than 2500 Å, and said source region and drain region having a thickness throughout which is greater than said channel region.

Claim 10

An active matrix assembly for a liquid crystal display device comprising: a plurality of liquid crystal driving electrodes arranged in a matrix of columns and rows; a plurality of data lines and address lines arranged in columns and rows of said matrix and intersecting each other to form a plurality of cross-over points; and a plurality of thin film transistors and liquid crystal driving electrodes located at the cross-over points of said data lines and address lines, said transistors for electrically coupling the data lines and address lines to each driving electrode and formed on a glass substrate using a non-monocrystalline silicon thin film; and wherein the thin film has a source region, a drain region and a channel region, formed in said thin film, said source region and drain region being spaced apart by said channel region, said channel region having a thickness of less than 2500 Å, and said source region and drain region having a thickness throughout which is greater than said channel region.

Claim 11

The active matrix assembly of claim 8, wherein the thin film layer comprises polycrystalline silicon.

Claim 12

The active matrix assembly of claim 9, wherein the polycrystalline silicon is intrinsic polycrystalline silicon.

Claim 13

The active matrix assembly of claim 8, wherein a gate insulating film on the silicon thin film comprises a thermally oxidized film of intrinsic polycrystalline silicon.

Claim 14

The active matrix assembly of claim 8, wherein the gate of said thin film transistors is formed of a material selected from the group consisting of polycrystalline silicon, metal silicofluoroxide or metal.

Claim 15

The active matrix assembly of claim 8, wherein the data lines and the driving electrodes comprise the same transparent conductive film.

Claim 16

The active matrix assembly of claim 13, wherein the transparent conductive film is selected from the group consisting of indium oxide, tin oxide and indium tin oxide.

Claim 17

The active matrix assembly of claim 8, wherein the channel region is an intrinsic channel region.

Claim 18

A metal-oxide-semiconductor transistor comprising: a glass insulating substrate; a thin film of non-monocrystalline silicon including a channel region of less than 2500 Å thickness disposed on said substrate; a source region and a drain region in said thin film silicon and spaced apart by said channel region, each source region and drain region formed from a dopant material and having throughout its region a thickness which is greater than the thickness of said channel region; an insulating film disposed on the surface of said thin film contacting at least a portion of the surface of each of said source, drain and channel regions; a gate disposed on said insulating film and between said source and drain regions; means for connecting said spaced apart source and drain regions and said gate electrode to external circuitry.

Claim 19

A metal-oxide-semiconductor transistor comprising: a glass insulating substrate; a thin film of non-monocrystalline silicon including a channel region of less than 2500 Å thickness disposed on said substrate; a source region and a drain region in said thin film silicon and spaced apart by said channel region, each source region and drain region formed from a dopant material and having throughout its region a thickness which is greater than the thickness of said channel region; an insulating film disposed on the surface of said thin film contacting at least a portion of the surface of each of said source, drain and channel regions; a gate disposed on said insulating film and between said source and drain regions; means for connecting said spaced apart source and drain regions and said gate electrode to external circuitry.

Claim 20

A metal oxide-semiconductor transistor comprising: a thin film of silicon selected from the group consisting of polycrystalline silicon and amorphous silicon including a channel region of less than 2500 Å thickness; a source region and a drain region in said thin film silicon and spaced apart by said channel region, each source region and drain region formed from a dopant material and having throughout its region a thickness which is greater than the thickness of said channel region; an insulating film disposed on the surface of said thin film contacting at least a portion of the surface of each of said source, drain and channel regions; a gate electrode disposed on said insulating film and between said source and drain regions; and means for connecting said spaced apart source and drain regions and said gate electrode to external circuitry.

Claim 21

A metal oxide-semiconductor transistor comprising: a thin film of silicon selected from the group consisting of polycrystalline silicon and amorphous silicon including a channel region of less than 2500 Å thickness; a source region and a drain region in said thin film silicon and spaced apart by said channel region, each source region and drain region formed from a dopant material and having throughout its region a thickness which is greater than the thickness of said channel region; an insulating film disposed on the surface of said thin film contacting at least a portion of the surface of each of said source, drain and channel regions; a gate electrode disposed on said insulating film and between said source and drain regions; and means for connecting said spaced apart source and drain regions and said gate electrode to external circuitry.