Process for preparing thin film transistor arrays

Claim 1

A process for manufacturing a thin film transistor array including a plurality of thin film transistors, each transistor having a source electrode (23, 25), a drain electrode (23, 25) and an insultated gate electrode (33) positioned with respect to a semiconductor pad (21), said plurality of thin film transistors arranged in rows and columns, each source electrode of each transistor in any given row being connected to a common bus conductor, each gate of each transistor in any given column being connected to a common bus conductor to form a matrix whereby any given transistor of the array can be addressed, each transistor having at least the interface of the semiconductor pad with the next adjacent subsequently deposited layers formed in a single vacuum pump-down, including the steps of forming the semiconductor pads (21) by depositing a semiconductor material through a mask (11) having openings (13) therein commensurate to the size, shape and relative position of the semiconductive pads to be deposited, moving the mask in a first direction parallel to one of the matrix axes for a specified distance, depositing a conductive material (23) through the openings in the mask to form a first , electrical contact to each semiconductive pad,movingthe mask in a direction 180° with respect to said first direction a distance of about twice the distance of the initial movement, depositing a conductive material (25) through the openings in the mask to form a second electrical contact to each semiconductive pad, depositing an insulating layer (27, 29) over at least the areas occupied by the semiconductor pads, removing the prepared structure from vacuum, applying discrete areas of conductive material (33) over the insulating layer to form the gate electrode of each transistor of the array, and forming the source bus conductors (31) and the gate bus conductors (35).