Patent US5124761A successfully refreshed from Google Patents.
US5124761A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor apparatus
Assignee: Sony Corp
•
Filing: 1989-01-20
•
Granted: 1992-06-23
•
Expires: 2009-01-20
Abstract
Abstract A semiconductor apparatus of the present invention comprises, as, for example, shown in FIG. 5, a semiconductor region (32) of first conductivity type formed on a semiconductor substrate (31), and a semiconductor region (34) of second conductivity type formed in the semiconductor region (32) of first conductivity type, in which a first electrode (38a) is formed on the semiconductor region (34) of second conductivity type to form a capacitance through a dielectric layer (37), a second electrode (38c) connected to the semiconductor region (32) of first conductivity type is provided and a third electrode (38b) connected to the semiconductor region (34) of second conductivity type is provided, whereby easiness (capacitor) can be prevented from being affected by a junction capacitance between semiconductor layers of different conductivity types.
Inventors
- 👤 Toshitaka Senuma
- 👤 Futao Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:18
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/819; H10D84/00; H10D84/80; H10D84/87
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
140 words
A semiconductor apparatus comprising a semiconductor region of first conductivity type formed on a semiconductor substrate and a semiconductor region of second conductivity type formed in said semiconductor region of first conductivity type, characterized by a semiconductor capacitance having a first electrode formed on said semiconductor region of second conductivity type to form a capacitance through a dielectric layer, a second electrode connected to said semiconductor region of first conductivity type and a third electrode connected to said semiconductor region of second conductivity type, and a buffer circuit, in which at least one of said first and third electrodes is connected to an input terminal of said buffer circuit, and said second electrode is connected to an output terminal of said buffer circuit, whereby a parasitic capacitor from said second electrode to ground is substantially short-circuited by said buffer circuit.
Claim 2
Dependent Claim
140 words
A semiconductor apparatus comprising a semiconductor region of first conductivity type formed on a semiconductor substrate and a semiconductor region of second conductivity type formed in said semiconductor region of first conductivity type, characterized by a semiconductor capacitance having a first electrode formed on said semiconductor region of second conductivity type to form a capacitance through a dielectric layer, a second electrode connected to said semiconductor region of first conductivity type and a third electrode connected to said semiconductor region of second conductivity type, and a buffer circuit, in which at least one of said first and third electrodes is connected to an input terminal of said buffer circuit, and said second electrode is connected to an output terminal of said buffer circuit, whereby a parasitic capacitor from said second electrode to ground is substantially short-circuited by said buffer circuit.
Claim 3
Dependent Claim
47 words
A semiconductor apparatus according to claim 1, in which a semiconductor region of first conductivity type is further formed on said semiconductor region of second conductivity type, and said semiconductor region of said first conductivity type and said semiconductor region of second conductivity type are electrically connected.
Claim 4
Dependent Claim
140 words
A semiconductor apparatus comprising a semiconductor region of second conductivity type formed on a semiconductor substrate consisting of a semiconductor material of first conductivity type, and a semiconductor region of first conductivity type formed on said semiconductor region of second conductivity type, characterized by a semiconductor capacitance having a first electrode formed on said semiconductor region of first conductivity type, a second electrode connected to said semiconductor region of first conductivity type and a third electrode connected to said semiconductor region of second conductivity type, and a buffer circuit, wherein at least one of said first and second electrodes is connected to an input terminal of said buffer circuit and said third electrode is connected to an output terminal of said buffer circuit, whereby a parasitic capacitor from said second electrode to ground is substantially short-circuited by said buffer circuit.
Claim 5
Dependent Claim
140 words
A semiconductor apparatus comprising a semiconductor region of second conductivity type formed on a semiconductor substrate consisting of a semiconductor material of first conductivity type, and a semiconductor region of first conductivity type formed on said semiconductor region of second conductivity type, characterized by a semiconductor capacitance having a first electrode formed on said semiconductor region of first conductivity type, a second electrode connected to said semiconductor region of first conductivity type and a third electrode connected to said semiconductor region of second conductivity type, and a buffer circuit, wherein at least one of said first and second electrodes is connected to an input terminal of said buffer circuit and said third electrode is connected to an output terminal of said buffer circuit, whereby a parasitic capacitor from said second electrode to ground is substantially short-circuited by said buffer circuit.
Claim 6
Dependent Claim
47 words
A semiconductor apparatus according to claim 3, characterized in that a semiconductor region of second conductivity type is further formed in said semiconductor region of first conductivity type, and said semiconductor region of second conductivity type and said semiconductor region of first conductivity type are electrically connected.
References Cited (Backward Citations)
JPS4883787A
Cited
US4151610A
Cited
US4214252A
Cited
JPS5543812A
Cited
JPS60170964A
Cited
JPS6124824A
Cited
US4672403A
Cited
JPS6292458A
Cited
JPS6292459A
Cited
JPS62142342A
Cited
JPS63155680A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |