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Patent US5124590A successfully refreshed from Google Patents.
US5124590A
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CMOS tri-mode input buffer
Assignee: Advanced Micro Devices Inc
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Filing: 1991-08-12
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Granted: 1992-06-23
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Expires: 2011-08-12
Abstract
Abstract A CMOS tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels includes an output stage (20), first output buffer (22), a second output buffer (24), a first inptu circuit (26), and a second input circuit (28). The output stage (20) generates first and second output signals (Q1, Q2) at the respective first and second output noes (16, 18). The first output buffer is responsive to the first output signal (Q1) for generating a first buffered input signal (U1) which is CMOS logic compatible. The second output buffer (24) is responsive to the second output signal (Q2) for generating second buffered output signal (U2) which is CMOS logic compatible.
Inventors
- 👤 Wen-Jung Liu
- 👤 Ann K. Woo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:01
CPC Classifications
H; H03; H03M; H03M5/00; H03M5/02; H03M5/16; H03M5/18
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
536 words
A CMOS tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels, said input buffer comprising: an output stage (20) formed of a first output transistor (M4) and a second output transistor (M3), said first output transistor (M4) having its drain connected to an upper supply potential (VDD) via a first load (29) and its source connected to a lower supply potential (VSS), said second output transistor (M3) having its drain connected to the upper supply potential (VDD) via a second load (31) and its source connected to the lower supply potential (VSS); said first output transistor (M4) having its drain also connected to a first output node (16) for generating a first output signal (Q1), said second output transistor having its drain also connected to a second output node (18) for generating a second output signal (Q2); a first output buffer (22) formed of first and second inverters (I1, I2), said first inverter (I1) having its input connected to said first output node (16) and its output connected to the input of said second inverter (I2), said second inverter (I2) having an output for generating a first buffered output signal (U1) which is CMOS logic compatible; a second output buffer (24) formed of third, fourth and fifth inverters (I3, I4, I5), said third inverter having its input connected to said second output node (18) and its output connected to the input of said fourth inverter (I4), said fifth inverter (I5) having its input connected to the output of said fourth inverter (I4) and an output for generating a second buffered output signal (U2) which is CMOS logic compatible; first input circuit means (26) formed of a voltage divider and a first input transistor (M6), said voltage divider being formed of first, second and third resistors (R1-R3), said first resistor (R1) having its one end connected to the upper supply potential (VDD) and its other end connected to a first internal node (A) and to an input pin (14) for receiving the input signal, said second resistor (R2) having its one end connected to the first internal node (A) and its other end connected to a second internal node (B) and to the gate of said second output transistor (M3), said third resistor (R3) having its one end connected to the second internal node (B) and its other end connected to a third internal node (Y), said first input transistor (M6) having its drain and gate connected together and to the third internal node (Y), the source of said first input transistor (M6) being connected to the lower supply potential (VSS); and second input circuit means (28) formed of a second input transistor (M5) and a fourth resistor (R4), said fourth resistor (R4) having its one end connected to the upper supply potential (VDD) and its other end connected to a fourth internal node (C) and to the gate of said first output transistor (M4), said second input transistor (M5) having its drain connected to the fourth internal node (C), its gate connected to the third internal node (Y), and its source connected to the lower supply potential (VSS).
Claim 2
Dependent Claim
536 words
A CMOS tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels, said input buffer comprising: an output stage (20) formed of a first output transistor (M4) and a second output transistor (M3), said first output transistor (M4) having its drain connected to an upper supply potential (VDD) via a first load (29) and its source connected to a lower supply potential (VSS), said second output transistor (M3) having its drain connected to the upper supply potential (VDD) via a second load (31) and its source connected to the lower supply potential (VSS); said first output transistor (M4) having its drain also connected to a first output node (16) for generating a first output signal (Q1), said second output transistor having its drain also connected to a second output node (18) for generating a second output signal (Q2); a first output buffer (22) formed of first and second inverters (I1, I2), said first inverter (I1) having its input connected to said first output node (16) and its output connected to the input of said second inverter (I2), said second inverter (I2) having an output for generating a first buffered output signal (U1) which is CMOS logic compatible; a second output buffer (24) formed of third, fourth and fifth inverters (I3, I4, I5), said third inverter having its input connected to said second output node (18) and its output connected to the input of said fourth inverter (I4), said fifth inverter (I5) having its input connected to the output of said fourth inverter (I4) and an output for generating a second buffered output signal (U2) which is CMOS logic compatible; first input circuit means (26) formed of a voltage divider and a first input transistor (M6), said voltage divider being formed of first, second and third resistors (R1-R3), said first resistor (R1) having its one end connected to the upper supply potential (VDD) and its other end connected to a first internal node (A) and to an input pin (14) for receiving the input signal, said second resistor (R2) having its one end connected to the first internal node (A) and its other end connected to a second internal node (B) and to the gate of said second output transistor (M3), said third resistor (R3) having its one end connected to the second internal node (B) and its other end connected to a third internal node (Y), said first input transistor (M6) having its drain and gate connected together and to the third internal node (Y), the source of said first input transistor (M6) being connected to the lower supply potential (VSS); and second input circuit means (28) formed of a second input transistor (M5) and a fourth resistor (R4), said fourth resistor (R4) having its one end connected to the upper supply potential (VDD) and its other end connected to a fourth internal node (C) and to the gate of said first output transistor (M4), said second input transistor (M5) having its drain connected to the fourth internal node (C), its gate connected to the third internal node (Y), and its source connected to the lower supply potential (VSS).
Claim 3
Dependent Claim
53 words
A CMOS tri-mode input buffer as claimed in claim 1, wherein said first load (29) is comprised of a first P-channel MOS transistor (M2) having its source connected to the upper supply potential (VDD), its gate connected to the lower supply potential (VSS), and its drain connected to the first output node (16).
Claim 4
Dependent Claim
53 words
A CMOS tri-mode input buffer as claimed in claim 2, wherein said second load (31) is comprised of a second P-channel MOS transistor (M1) having its source connected to the upper supply potential (VDD), its gate connected to the lower supply potential (VSS) and its drain connected to the second output node (18).
Claim 5
Dependent Claim
31 words
A CMOS tri-mode input buffer as claimed in claim 1, wherein said upper supply potential (VDD) is at +5.0 volts, and wherein said lower supply potential (VSS) is at 0 volts.
Claim 6
Dependent Claim
23 words
A CMOS tri-mode input buffer as claimed in claim 1, wherein said first and second output transistors (M4, M3) are N-channel MOS transistors.
Claim 7
Dependent Claim
21 words
A CMOS tri-mode input buffer as claimed in claim 1, wherein said first input transistor (M6) is an N-channel MOS transistor.
Claim 8
Dependent Claim
21 words
A CMOS tri-mode input buffer as claimed in claim 1, wherein said second input transistor (M5) is an N-channel MOS transistor.
Claim 9
Dependent Claim
79 words
A CMOS tri-mode input buffer as claimed in claim 1, wherein said input signal in a low logic region defining a first input voltage level when it is varied between 0 to VDD/4, said input signal is in a floating region defining a second input voltage level when it is varied between VDD/4 to 3VDD/4, and said input signal is in a high logic region defining a third input voltage level when it is varied between 3VDD/4 to VDD.
Claim 10
Dependent Claim
36 words
A CMOS tri-mode input buffer as claimed in claim 1, wherein the value of said resistors (R1-R3) are selected so that the voltage level is at approximately VDD/2 when said input pin (14) is left unconnected.
Claim 11
Dependent Claim
404 words
A tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels, said input buffer comprising: an output stage (20) formed of a first output transistor (M4) and a second output transistor (M3), said first output transistor (M4) having its drain connected to an upper supply potential (VDD) via a first load (29) and its source connected to a lower supply potential (VSS), said second output transistor (M3) having its drain connected to the upper supply potential (VDD) via a second load (31) and its source connected to the lower supply potential (VSS); said first output transistor (M4) having its drain also connected to a first output node (16) for generating a first output signal (Q1), said second output transistor having its drain also connected to a second output node (18) for generating a second output signal (Q2); first input circuit means (26) formed of a voltage divider and a first input transistor (M6), said voltage divider being formed of first, second and third resistors (R1-R3), said first resistor (R1) having its one end connected to the upper supply potential (VDD) and its other end connected to a first internal node (A) and to an input pin (14) for receiving the input signal, said second resistor (R2) having its one end connected to the first internal node (A) and its other end connected to a second internal node (B) and to the gate of said second output transistor (M3), said third resistor (R3) having its one end connected to the second internal node (B) and its other end connected to a third internal node (Y), said first input transistor (M6) having its drain and gate connected together and to the third internal node (Y), the source of said first input transistor (M6) being connected to the lower supply potential (VSS); and second input circuit means (28) formed of a second input transistor (M5) and a fourth resistor (R4), said fourth resistor (R4) having its one end connected to the upper supply potential (VDD) and its other end connected to a fourth internal node (C) and to the gate of said first output transistor (M4), said second input transistor (M5) having its drain connected to the fourth internal node (C), its gate connected to the third internal node (Y), and its source connected to the lower supply potential (VSS).
Claim 12
Dependent Claim
404 words
A tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels, said input buffer comprising: an output stage (20) formed of a first output transistor (M4) and a second output transistor (M3), said first output transistor (M4) having its drain connected to an upper supply potential (VDD) via a first load (29) and its source connected to a lower supply potential (VSS), said second output transistor (M3) having its drain connected to the upper supply potential (VDD) via a second load (31) and its source connected to the lower supply potential (VSS); said first output transistor (M4) having its drain also connected to a first output node (16) for generating a first output signal (Q1), said second output transistor having its drain also connected to a second output node (18) for generating a second output signal (Q2); first input circuit means (26) formed of a voltage divider and a first input transistor (M6), said voltage divider being formed of first, second and third resistors (R1-R3), said first resistor (R1) having its one end connected to the upper supply potential (VDD) and its other end connected to a first internal node (A) and to an input pin (14) for receiving the input signal, said second resistor (R2) having its one end connected to the first internal node (A) and its other end connected to a second internal node (B) and to the gate of said second output transistor (M3), said third resistor (R3) having its one end connected to the second internal node (B) and its other end connected to a third internal node (Y), said first input transistor (M6) having its drain and gate connected together and to the third internal node (Y), the source of said first input transistor (M6) being connected to the lower supply potential (VSS); and second input circuit means (28) formed of a second input transistor (M5) and a fourth resistor (R4), said fourth resistor (R4) having its one end connected to the upper supply potential (VDD) and its other end connected to a fourth internal node (C) and to the gate of said first output transistor (M4), said second input transistor (M5) having its drain connected to the fourth internal node (C), its gate connected to the third internal node (Y), and its source connected to the lower supply potential (VSS).
Claim 13
Dependent Claim
52 words
A tri-mode input buffer as claimed in claim 10, wherein said first load (29) is comprised of a first P-channel MOS transistor (M2) having its source connected to the upper supply potential (VDD), its gate connected to the lower supply potential (VSS), and its drain connected to the first output node (16).
Claim 14
Dependent Claim
52 words
A tri-mode input buffer as claimed in claim 11, wherein said second load (31) is comprised of a second P-channel MOS transistor (M1) having its source connected to the upper supply potential (VDD), its gate connected to the lower supply potential (VSS) and its drain connected to the second output node (18).
Claim 15
Dependent Claim
30 words
A tri-mode input buffer as claimed in claim 10, wherein said upper supply potential (VDD) is at +5.0 volts, and wherein said lower supply potential (VSS) is at 0 volts.
Claim 16
Dependent Claim
22 words
A tri-mode input buffer as claimed in claim 10, wherein said first and second output transistors (M4, M3) are N-channel MOS transistors.
Claim 17
Dependent Claim
20 words
A tri-mode input buffer as claimed in claim 10, wherein said first input transistor (M6) is an N-channel MOS transistor.
Claim 18
Dependent Claim
20 words
A tri-mode input buffer as claimed in claim 10, wherein said second input transistor (M5) is an N-channel MOS transistor.
Claim 19
Dependent Claim
78 words
A tri-mode input buffer as claimed in claim 10, wherein said input signal in a low logic region defining a first input voltage level when it is varied between 0 to VDD/4, said input signal is in a floating region defining a second input voltage level when it is varied between VDD/4 to 3VDD/4, and said input signal is in a high logic region defining a third input voltage level when it is varied between 3VDD/4 to VDD.
Claim 20
Dependent Claim
35 words
A tri-mode input buffer as claimed in claim 10, wherein the value of said resistors (R1-R3) are selected so that the voltage level is at approximately VDD/2 when said input pin (14) is left unconnected.
Claim 21
Dependent Claim
233 words
A tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels, said input buffer comprising: an output stage (20) formed of a first output transistor (M4) and a second output transistor (M3), said first output transistor (M4) having its drain connected to an upper supply potential (VDD) via a first load (29) and its source connected to a lower supply potential (VSS), said second output transistor (M3) having its drain connected to the upper supply potential (VDD) via a second load (31) and its source connected to the lower supply potential (VSS); said first output transistor (M4) having its drain also connected to a first output node (16) for generating a first output signal (Q1), said second output transistor having its drain also connected to a second output node (18) for generating a second output signal (Q2); first input means responsive to an input signal for establishing first and second control voltages at respective first and second internal nodes; second input means responsive to said second control voltage at said second internal node for generating a third control signal at a third internal node; and the gate of said first output transistor (M4) being responsive to said third control voltage and the gate of said second output transistor (M3) being responsive to said first control voltage.
Claim 22
Dependent Claim
233 words
A tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels, said input buffer comprising: an output stage (20) formed of a first output transistor (M4) and a second output transistor (M3), said first output transistor (M4) having its drain connected to an upper supply potential (VDD) via a first load (29) and its source connected to a lower supply potential (VSS), said second output transistor (M3) having its drain connected to the upper supply potential (VDD) via a second load (31) and its source connected to the lower supply potential (VSS); said first output transistor (M4) having its drain also connected to a first output node (16) for generating a first output signal (Q1), said second output transistor having its drain also connected to a second output node (18) for generating a second output signal (Q2); first input means responsive to an input signal for establishing first and second control voltages at respective first and second internal nodes; second input means responsive to said second control voltage at said second internal node for generating a third control signal at a third internal node; and the gate of said first output transistor (M4) being responsive to said third control voltage and the gate of said second output transistor (M3) being responsive to said first control voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |