Dual-charge-pump bandwidth-switched phase-locked loop

Claim 2

A phase-locked loop comprising: A) a variable-frequency oscillator, adapted for application thereto of a frequency-control signal, for generating an oscillator output whose frequency is determined by the value of the frequency-control signal; B) a phase detector adapted for application thereto of a input signal and responsive to the oscillator output to generate a phase-detector output indicative of the phase relationship between the input signal and the oscillator output; and C) a proportional-plus-integral feed-forward network responsive to the phase-detector output to generate a frequency-control signal and apply it to the oscillator, the feed-forward network comprising: i) a proportional-plus-integral path for generating in the frequency-control signal proportional and integral components that are proportional, in accordance with separately adjustable proportional-component and integral-component gains, respectively, to the phase-detector output and the integral thereof; and ii) gain-adjustment circuitry for making different variations in the integral-component and proportional-component gains.

Claim 3

A phase-locked loop as defined in claim 1 wherein the gain-adjustment circuitry varies the proportional-component gain with the integral-component gain but through a dynamic range less than that through which it varies the integral-component gain.

Claim 4

A phase-locked loop as defined in claim 2 wherein: A) the proportional-plus-integral path includes: i) two separate charge pumps controlled by the phase-detector output; ii) a separate parallel signal path associated with each charge pump and driven by its associated charge pump to generate a parallel-path output; and iii) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and B) the gain-adjustment circuitry varies the gain by varying the charge-pump currents.

Claim 5

A phase-locked as defined in claim 3 wherein one of the parallel signal paths is a substantially proportional path and the other is a substantially integral path.

Claim 6

A phase-locked as defined in claim 3 wherein the gain-adjustment circuitry varies the proportional-component gain in proportion to the square root of the integral-component gain.

Claim 7

A phase-locked loop as defined in claim 2 wherein the gain-adjustment circuitry varies the proportional-component gain in proportion to the square root of the integral-component gain.

Claim 8

A phase-locked loop as defined in claim 1 wherein: A) the proportional-plus-integral path includes: i) two separate charge pumps controlled by the phase-detector output; ii) a separate parallel signal path associated with each charge pump and driven by its associated charge pump to generate a parallel-path output; and iii) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and B) the gain-adjustment circuitry varies the gain by varying the charge-pump currents.

Claim 9

A phase-locked loop as defined in claim 7 wherein one of the parallel signal paths is a substantially proportional path and the other is a substantially integral path.

Claim 10

A phase-locked loop as defined in claim 1 wherein: A) the proportional-plus-integral path includes: i) separate parallel signal paths responsive to the phase-detector output to generate respective parallel-path outputs; and ii) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and B) the gain-adjustment circuitry separately varies the gains that characterize the parts of the response of the frequency-control signal to the phase-detector output that result from the different parallel signal paths.

Claim 11

A phase-locked loop as defined in claim 9 wherein one of the parallel signal paths is a substantially proportional path and the other is a substantially integral path.

Claim 12

A phase-locked loop comprising: A) a variable-frequency oscillator, adapted for application thereto of a frequency-control signal, for generating an oscillator output whose frequency is determined by the value of the frequency-control signal; B) a phase detector adapted for application thereto of an input signal and responsive to the oscillator output to generate a phase-detector output indicative of the phase relationship between the input signal and the oscillator output; and c) a proportional-plus-integral feed-forward network responsive to the phase-detector output to generate a frequency-control signal and apply it to the oscillator, the feed-forward network comprising: i) a proportional-plus-integral path for generating in the frequency-control signal proportional and integral components that are proportional, in accordance with separately adjustable proportional-component and integral-component gains, respectively, to the phase-detector output and the integral thereof, the proportional-plus-integral path including: a) two separate charge pumps controlled by the phase-detector output, b) a separate parallel signal path associated with each charge pump and driven by its associated charge pump to generate a parallel-path output, one of the parallel signal paths being a substantially proportional path and the other being a substantially integral path; and c) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and ii) gain-adjustment circuitry for so varying the charge-pump currents as to vary the proportional-component gain in proportion to the square root of the integral-component gain.

Claim 13

A phase-locked loop comprising: A) a variable-frequency oscillator, adapted for application thereto of a frequency-control signal, for generating an oscillator output whose frequency is determined by the value of the frequency-control signal; B) a phase detector adapted for application thereto of an input signal and responsive to the oscillator output to generate a phase-detector output indicative of the phase relationship between the input signal and the oscillator output; and c) a proportional-plus-integral feed-forward network responsive to the phase-detector output to generate a frequency-control signal and apply it to the oscillator, the feed-forward network comprising: i) a proportional-plus-integral path for generating in the frequency-control signal proportional and integral components that are proportional, in accordance with separately adjustable proportional-component and integral-component gains, respectively, to the phase-detector output and the integral thereof, the proportional-plus-integral path including: a) two separate charge pumps controlled by the phase-detector output, b) a separate parallel signal path associated with each charge pump and driven by its associated charge pump to generate a parallel-path output, one of the parallel signal paths being a substantially proportional path and the other being a substantially integral path; and c) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and ii) gain-adjustment circuitry for so varying the charge-pump currents as to vary the proportional-component gain in proportion to the square root of the integral-component gain.

Claim 14

A disk drive comprising: A) a head-reading mechanism for reading a magnetic disk and generating in response thereto a read signal comprising pulses that represent timing and data information contained on the disk; B) a phase-locked loop comprising: i) a variable-frequency oscillator, adapted for application thereto of a frequency-control signal, for generating an oscillator output whose frequency is determined by the value of the frequency-control signal; ii) a phase detector responsive to the read signal and the oscillator output to generate a phase-detector output indicative of the phase relationship between the read signal and the oscillator output; and iii) a proportional-plus-integral feed-forward network responsive to the phase-detector output to generate a frequency-control signal and apply it to the oscillator, the feed-forward network comprising: a) a proportional-plus-integral path for generating in the frequency-control signal proportional and integral components that are proportional, in accordance with separately adjustable proportional-component and integral-component gains, respectively, to the phase-detector output and the integral thereof; and b) a gain-adjustment circuitry for making different variations in the integral-component and proportional-component gains; and C) a data-extraction circuit responsive to the read signal and the oscillator output for extracting the data information from the read signal in accordance with timing established by the oscillator output.

Claim 15

A disk drive comprising: A) a head-reading mechanism for reading a magnetic disk and generating in response thereto a read signal comprising pulses that represent timing and data information contained on the disk; B) a phase-locked loop comprising: i) a variable-frequency oscillator, adapted for application thereto of a frequency-control signal, for generating an oscillator output whose frequency is determined by the value of the frequency-control signal; ii) a phase detector responsive to the read signal and the oscillator output to generate a phase-detector output indicative of the phase relationship between the read signal and the oscillator output; and iii) a proportional-plus-integral feed-forward network responsive to the phase-detector output to generate a frequency-control signal and apply it to the oscillator, the feed-forward network comprising: a) a proportional-plus-integral path for generating in the frequency-control signal proportional and integral components that are proportional, in accordance with separately adjustable proportional-component and integral-component gains, respectively, to the phase-detector output and the integral thereof; and b) a gain-adjustment circuitry for making different variations in the integral-component and proportional-component gains; and C) a data-extraction circuit responsive to the read signal and the oscillator output for extracting the data information from the read signal in accordance with timing established by the oscillator output.

Claim 16

A disk drive as defined in claim 12 wherein the gain-adjustment circuitry varies the proportional-component gain with the integral-component gain but through a dynamic range less than that through which it varies the integral-component gain.

Claim 17

A disk drive as defined in claim 13 wherein: A) the proportional-plus-integral path includes: i) two separate charge pumps controlled by the phase-detector output; ii) a separate parallel signal path associated with each charge pump and driven by its associated charge pump to generate a parallel-path output; and iii) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and B) the gain-adjustment circuitry varies the gain by varying the charge-pump currents.

Claim 18

A disk drive as defined in claim 14 wherein one of the parallel signal paths is a substantially proportional path and the other is a substantially integral path.

Claim 19

A disk drive as defined in claim 14 wherein the gain-adjustment circuitry varies the proportional-component gain in proportion to the square root of the integral-component gain.

Claim 20

A disk drive as defined in claim 13 wherein the gain-adjustment circuitry varies the proportional-component gain in proportion to the square root of the integral-component gain.

Claim 21

A disk drive as defined in claim 12 wherein: A) the proportional-plus-integral path includes: i) two separate charge pumps controlled by the phase-detector output; ii) a separate parallel signal path associated with each charge pump and driven by its associated charge pump to generate a parallel-path output; and iii) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and B) the gain-adjustment circuitry varies the gain by varying the charge-pump currents.

Claim 22

A disk drive as defined in claim 18 wherein one of the parallel signal paths is a substantially proportional path and the other is a substantially integral path.

Claim 23

A disk drive as defined in claim 12 wherein: A) the proportional-plus-integral path includes: i) separate parallel signal paths responsive to the phase-detector output to generate respective parallel-path outputs; and ii) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and B) the gain-adjustment circuitry separately varies the gains that characterize the parts of the response of the frequency-control signal to the phase-detector output that result from the different parallel signal paths.

Claim 24

A disk drive as defined in claim 20 wherein one of the parallel signal paths is a substantially proportional path and the other is a substantially integral path.

Claim 25

A disk drive comprising: A) a head-reading mechanism for reading a magnetic disk and generating in response thereto a read signal comprising pulses that represent timing and data information contained on the disk; B) a phase-locked loop comprising: i) a variable-frequency oscillator; adapted for application thereto of a frequency-control signal, for generating an oscillator output whose frequency is determined by the value of the frequency-control signal; ii) a phase detector responsive to the read signal and the oscillator output to generate a phase-detector output indicative of the phase relationship between the read signal and the oscillator output; and iii) a proportional-plus-integral feed-forward network responsive to the phase-detector output to generate a frequency-control signal and apply it to the oscillator, the feed-forward network comprising: a) a proportional-plus-integral path for generating in the frequency-control signal proportional and integral components that are proportional, in accordance with separately adjustable proportional-component and integral-component gains, respectively, to the phase-detector output and the integral thereof, the proportional-plus-integral path including: 1) two separate charge pumps controlled by the phase-detector output, 2) a separate parallel signal path associated with each charge pump and driven by its associated charge pump to generate a parallel-path output, one of the parallel signal paths being a substantially proportional path and the other being a substantially integral path; and 3) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and b) gain-adjustment circuitry for so varying the charge-pump currents as to vary the proportional-component gain in proportion to the square root of the integral-component gain; and C) a data-extraction circuit responsive to the read signal and the oscillator output for extracting the data information from the read signal in accordance with timing established by the oscillator output.

Claim 26

A disk drive comprising: A) a head-reading mechanism for reading a magnetic disk and generating in response thereto a read signal comprising pulses that represent timing and data information contained on the disk; B) a phase-locked loop comprising: i) a variable-frequency oscillator; adapted for application thereto of a frequency-control signal, for generating an oscillator output whose frequency is determined by the value of the frequency-control signal; ii) a phase detector responsive to the read signal and the oscillator output to generate a phase-detector output indicative of the phase relationship between the read signal and the oscillator output; and iii) a proportional-plus-integral feed-forward network responsive to the phase-detector output to generate a frequency-control signal and apply it to the oscillator, the feed-forward network comprising: a) a proportional-plus-integral path for generating in the frequency-control signal proportional and integral components that are proportional, in accordance with separately adjustable proportional-component and integral-component gains, respectively, to the phase-detector output and the integral thereof, the proportional-plus-integral path including: 1) two separate charge pumps controlled by the phase-detector output, 2) a separate parallel signal path associated with each charge pump and driven by its associated charge pump to generate a parallel-path output, one of the parallel signal paths being a substantially proportional path and the other being a substantially integral path; and 3) a summing circuit that adds the parallel-path outputs to generate the proportional and integral components of the frequency-control signal; and b) gain-adjustment circuitry for so varying the charge-pump currents as to vary the proportional-component gain in proportion to the square root of the integral-component gain; and C) a data-extraction circuit responsive to the read signal and the oscillator output for extracting the data information from the read signal in accordance with timing established by the oscillator output.