Patent US5119152A successfully refreshed from Google Patents.
US5119152A
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MOS semiconductor device having LDD structure
Assignee: Toshiba Corp
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Filing: 1991-03-19
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Granted: 1992-06-02
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Expires: 2011-03-19
Abstract
Abstract Disclosed is a MOS type semiconductor device, particularly, a MOS type transistor of an LDD structure, which is featured in the side wall structure which covers the side surface of a gate electrode formed on the surface of a semiconductor substrate with a first insulating film interposed therebetween. The semiconductor device comprises source and drain regions of a double diffusion structure consisting of an impurity diffusion region of a relatively low impurity concentration formed apart from the gate electrode in the surface region of the semiconductor substrate and positioned below the side wall region of the gate electrode, and an impurity diffusion region of a relatively high impurity concentration formed in the surface region of the semiconductor substrate and positioned outside the gate electrode. The side wall structure of the gate electrode comprises a first material layer having a first dielectric constant and formed as a side wall of the gate electrode on the impurity diffusion region of the relatively low impurity concentration, and a second material layer having a second dielectric constant small than the first dielectric constant and formed as a side wall of the gate electrode to cover the first material layer, said second material layer being positioned to cover the boundary region between the impurity diffusion regions of the low and high impurity concentrations.
Inventors
- 👤 Tomohisa Mizuno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D64/00; H10D64/01; H10D64/021
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
176 words
A MOS type semiconductor device, comprising: a first insulating film formed to cover a surface of a semiconductor substrate; a gate electrode selectively formed on said first insulating film; source and drain regions of a double diffusion structure consisting of a first impurity diffusion region formed in the surface region of the semiconductor substrate and positioned below the side wall region of the gate electrode, and a second impurity diffusion region of an impurity concentration higher than that of the first impurity diffusion region, and formed in the surface region of the semiconductor substrate and positioned so as to substantially not underlie the gate electrode; a first material layer having a first dielectric constant and positioned adjacent to the side wall of the gate electrode and substantially above the first impurity diffusion region; and a second material layer having a second dielectric constant less than the first dielectric constant and positioned adjacent to the first material layer, said second material layer being positioned substantially above the boundary region between the first and second impurity diffusion regions.
Claim 2
Dependent Claim
176 words
A MOS type semiconductor device, comprising: a first insulating film formed to cover a surface of a semiconductor substrate; a gate electrode selectively formed on said first insulating film; source and drain regions of a double diffusion structure consisting of a first impurity diffusion region formed in the surface region of the semiconductor substrate and positioned below the side wall region of the gate electrode, and a second impurity diffusion region of an impurity concentration higher than that of the first impurity diffusion region, and formed in the surface region of the semiconductor substrate and positioned so as to substantially not underlie the gate electrode; a first material layer having a first dielectric constant and positioned adjacent to the side wall of the gate electrode and substantially above the first impurity diffusion region; and a second material layer having a second dielectric constant less than the first dielectric constant and positioned adjacent to the first material layer, said second material layer being positioned substantially above the boundary region between the first and second impurity diffusion regions.
Claim 3
Dependent Claim
24 words
The MOS type semiconductor device according to claim 1, wherein each of the first and second material layers is formed of an insulating material.
Claim 4
Dependent Claim
43 words
The MOS type semiconductor device according to claim 1, wherein the second material layer is formed of SiO 2 , and the first material layer is formed of an insulating material having a specific dielectric constant larger than that of SiO 2 .
Claim 5
Dependent Claim
32 words
The MOS type semiconductor device according to claim 1, wherein the first material layer is formed of Ta 2 O 5 and the second material layer is formed of SiO 2 .
Claim 6
Dependent Claim
32 words
The MOS type semiconductor device according to claim 1, wherein the first material layer is formed of Si 3 N 4 and the second material layer is formed of SiO 2 .
Claim 7
Dependent Claim
38 words
The MOS type semiconductor device according to claim 1, wherein the first material layer is formed of PZT having a large dielectric constant and the second material layer is formed of polytetrafluoro ethylene having a small dielectric constant.
Claim 8
Dependent Claim
45 words
The MOS type semiconductor device according to claim 1, wherein the first insulating film is interposed between the first material layer and the semiconductor substrate, positioned at least below the gate electrode, and has a band gap greater than that of the first material layer.
Claim 9
Dependent Claim
47 words
The MOS type semiconductor device according to claim 1, wherein the first insulating film is formed of SiO 2 and has a thickness greater than the mean free path of the hot carrier in at least the region between the first material layer and the semiconductor substrate.
Claim 10
Dependent Claim
220 words
The MOS type semiconductor device having an LDD structure, comprising: a first insulating film formed to cover a surface of a silicon substrate of a first conductivity type; a gate electrode selectively formed on said first insulating film; source and drain regions of a double diffusion structure consisting of a first impurity diffusion region formed in the surface region of the semiconductor substrate and positioned below the side wall region of the gate electrode, said first impurity diffusion region having a second conductivity type, and a second impurity diffusion region of an impurity concentration higher than that of the first impurity diffusion region, and formed in the surface region of the semiconductor substrate in contact with the first impurity diffusion region and positioned so as to substantially not underlie the gate electrode, said second impurity diffusion region having a second conductivity type; a first side wall of the gate electrode positioned adjacent to the side surface of the gate electrode, having a first dielectric constant and positioned substantially above the first impurity diffusion region; and a second side wall of the gate electrode positioned adjacent to the first side wall of the gate electrode, having a second dielectric constant less than the first dielectric constant, and formed substantially above the boundary region between the first and second impurity diffusion regions.
Claim 11
Dependent Claim
220 words
The MOS type semiconductor device having an LDD structure, comprising: a first insulating film formed to cover a surface of a silicon substrate of a first conductivity type; a gate electrode selectively formed on said first insulating film; source and drain regions of a double diffusion structure consisting of a first impurity diffusion region formed in the surface region of the semiconductor substrate and positioned below the side wall region of the gate electrode, said first impurity diffusion region having a second conductivity type, and a second impurity diffusion region of an impurity concentration higher than that of the first impurity diffusion region, and formed in the surface region of the semiconductor substrate in contact with the first impurity diffusion region and positioned so as to substantially not underlie the gate electrode, said second impurity diffusion region having a second conductivity type; a first side wall of the gate electrode positioned adjacent to the side surface of the gate electrode, having a first dielectric constant and positioned substantially above the first impurity diffusion region; and a second side wall of the gate electrode positioned adjacent to the first side wall of the gate electrode, having a second dielectric constant less than the first dielectric constant, and formed substantially above the boundary region between the first and second impurity diffusion regions.
Claim 12
Dependent Claim
28 words
The MOS type semiconductor device according to claim 9, wherein each of the first and second side walls of the gate electrode is formed of an insulating material.
Claim 13
Dependent Claim
51 words
The MOS type semiconductor device according to claim 9, wherein the second side wall of the gate electrode is formed of SiO 2 , and the first side wall of the gate electrode is formed of an insulating material having a specific dielectric constant larger than that of SiO 2 .
Claim 14
Dependent Claim
40 words
The MOS type semiconductor device according to claim 9, wherein the first side wall of the gate electrode is formed of Ta 2 O 5 and the second side wall of the gate electrode is formed of SiO 2 .
Claim 15
Dependent Claim
32 words
The MOS type semiconductor device according to claim 9, wherein the first material layer is formed of Si 3 N 4 and the second material layer is formed of SiO 2 .
Claim 16
Dependent Claim
46 words
The MOS type semiconductor device according to claim 9, wherein the first side wall of the gate electrode is formed of PZT having a large dielectric constant and the second side wall of the gate electrode is formed of polytetrafluoro ethylene having a small dielectric constant.
Claim 17
Dependent Claim
53 words
The MOS type semiconductor device according to claim 9, wherein the first insulating film is interposed between the first side wall of the gate electrode and the semiconductor substrate, positioned at least below the gate electrode, and has a band gap greater than that of the first side wall of the gate electrode.
Claim 18
Dependent Claim
51 words
The MOS type semiconductor device according to claim 9, wherein the first insulating film is formed of SiO 2 and has a thickness greater than the mean free path of the hot carrier in at least the region between the first side wall of the gate electrode and the semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-02 | 1995-12-02 | 1996-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-02 | 1999-12-02 | 2000-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-02 | 2003-12-02 | 2004-06-02 | $7700.00 | Window Closed / Lapsed |