US5118968A
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Special mode activation circuit for selectively activating a special mode circuit of a semiconductor integrated circuit device
Assignee: Micron Technology Inc
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Filing: 1990-09-12
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Granted: 1992-06-02
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Expires: 2010-09-12
Abstract
Abstract A special mode activation circuit is disclosed for activating a special mode circuit within a semiconductor integrated circuit when the voltage of an input signal at an input terminal of the integrated circuit reaches a special high voltage level that is substantially above a low voltage level range of signals normally associated with binary logic levels. The special mode activation circuit comprises a voltage reduction subcircuit, a voltage detection subcircuit, and an active pullup subcircuit. The voltage reduction subcircuit reduces the voltage of the input signal to generate a reduced voltage input signal. The voltage detection subcircuit is responsive to the reduced voltage signal to prevent activation of the special mode circuit when the reduced voltage input signal is less than a preset threshold value and to activate the special mode circuit when reduced voltage input signal exceeds the preset threshold value. The active pullup subcircuit maintains the voltage of the reduced voltage input signal above a minimum voltage to (1) prevent leakage current through the voltage reduction subcircuit, (2) reduce the voltage change required in the reduced voltage input signal to activate the special mode circuit, and (3) reduce the possibility of induced latchup.
Inventors
- 👤 Kurt P. Douglas
- 👤 Wen-Foo Chern
- 👤 Vijaya B. Wickremarachchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:47
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534; H03K17/00; H03K17/30; H03K17/302
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
284 words
In a semiconductor integrated circuit device having both an operational circuit and a normally deactivated special mode circuit connected in common to an input terminal to receive an input signal normally of low voltage level associated with binary logic values that is processed by the operational circuit, a special mode activation circuit operatively connected to the input terminal and the special mode circuit for maintaining the special mode circuit deactivated when the input signal is of the low voltage level and for activating the special mode circuit when the input signal is changed to a special high voltage level, said special mode activation circuit comprising: a voltage reduction subcircuit for reducing the voltage of the input signal by a preset voltage value to generate a reduced voltage input signal; a voltage detection subcircuit operatively connected to the special mode circuit and responsive to the reduced voltage input signal for preventing activation of the special mode circuit when the voltage of the reduced voltage input signal is less than a preset threshold value and for activating the special mode circuit when the voltage of the reduced voltage input signal exceeds the preset threshold value; an active pullup subcircuit which maintains the voltage of the reduced voltage input signal above a minimum voltage, the minimum voltage being below the preset thresold value; and wherein the sum of the preset voltage value of the voltage reduction subcircuit and the preset threshold value of the voltage detection subcircuit is substantially greater than the low voltage level normally associated with binary logic values, in which the special high voltage level input signal must be equal to or greater than such sum in order to activate the special mode circuit.
Claim 2
Dependent Claim
284 words
In a semiconductor integrated circuit device having both an operational circuit and a normally deactivated special mode circuit connected in common to an input terminal to receive an input signal normally of low voltage level associated with binary logic values that is processed by the operational circuit, a special mode activation circuit operatively connected to the input terminal and the special mode circuit for maintaining the special mode circuit deactivated when the input signal is of the low voltage level and for activating the special mode circuit when the input signal is changed to a special high voltage level, said special mode activation circuit comprising: a voltage reduction subcircuit for reducing the voltage of the input signal by a preset voltage value to generate a reduced voltage input signal; a voltage detection subcircuit operatively connected to the special mode circuit and responsive to the reduced voltage input signal for preventing activation of the special mode circuit when the voltage of the reduced voltage input signal is less than a preset threshold value and for activating the special mode circuit when the voltage of the reduced voltage input signal exceeds the preset threshold value; an active pullup subcircuit which maintains the voltage of the reduced voltage input signal above a minimum voltage, the minimum voltage being below the preset thresold value; and wherein the sum of the preset voltage value of the voltage reduction subcircuit and the preset threshold value of the voltage detection subcircuit is substantially greater than the low voltage level normally associated with binary logic values, in which the special high voltage level input signal must be equal to or greater than such sum in order to activate the special mode circuit.
Claim 3
Dependent Claim
23 words
In the semiconductor integrated circuit device of claim 1, wherein the preset threshold value exceeds the voltage normally associated with binary logic values.
Claim 4
Dependent Claim
34 words
In the semiconductor integrated circuit device of claim 1, wherein the voltage detection subcircuit operates from a postive supply voltage and the preset threshold value exceeds the positive supply voltage by a fixed value.
Claim 5
Dependent Claim
23 words
In the semiconductor integrated circuit device of claim 1, wherein the preset threhold value exceeds the voltage normally associated with binary logic values.
Claim 6
Dependent Claim
37 words
In the semiconductor integrated circuit device of claim 1 wherein the active pullup subcircuit comprises a MOSFET transistor having a gate and drain connected to a voltage reference and a source connected to the reduced voltage signal.
Claim 7
Dependent Claim
23 words
In the semiconductor integrated circuit device of claim 1, wherein the voltage reduction subcircuit includes means for preventing reverse flow of current therethrough.
Claim 8
Dependent Claim
39 words
In the semiconductor integrated circuit device of claim 1 wherein the voltage reduction subcircuit includes a plurality of serially connected transistors configured to function as diodes for generating the reduced voltage input signal and for preventing reverse current therethrough.
Claim 9
Dependent Claim
35 words
In the semiconductor integrated circuit device of claim 7 wherein the voltage reduction subcircuit includes at least three serially connected diode-acting transistors for generating the reduced voltage input signal and for preventing reverse current therethrough.
Claim 10
Dependent Claim
28 words
In the semiconductor integrated circuit device of claim 7 wherein each of the series-connected diode-acting transistors drops an incremental voltage of between 0.3 volts and 1.0 volts inclusive.
Claim 11
Dependent Claim
29 words
In the semiconductor integrated circuit device of claim 1, the active pullup subcircuit comprising semiconductor diode means for unidirectionally conducting from a voltage reference to the reduced voltage signal.
Claim 12
Dependent Claim
46 words
In the semiconductor integrated circuit device of claim 1 wherein the sum of the preset voltage value of the voltage reduction subcircuit and the preset threshold value of the voltage detection subcircuit is greater than twice the low level voltage normally associated with binary logic values.
Claim 13
Dependent Claim
139 words
In the semiconductor intergrated circuit device of claim 1, wherein: the voltage reduction subcircuit comprises a plurality of serially connected diode voltage reduction means for generating the reduced voltage input signal and for preventing reverse current therethrough; the voltage detection subcircuit comprises first and second MOSFET transistors, the first and second transistors having sources connected in common to form an activation line, each transistor having a gate connected to a voltage reference, the second transistor having a drain connected to ground, and the first transistors having a drain connected to the reduced voltage input signal, the transistors being adapted to activate the special mode circuit through the activation line when the reduced voltage input signal exceeds the preset threshold value, the preset threhold value being approximately equal to the voltage reference plus the threshold voltage of the first transistor.
Claim 14
Dependent Claim
74 words
In the semiconductor integrated circuit device of claim 12, each diode voltage reduction means comprising a MOSFET transistor having a source, a drain, and a gate, wherein the drain and gate are connected in common to prevent reverse current from the source to the drain and wherein forward current from the drain to the source flows only when the drain has a voltage with respect to the source which exceeds the transistor threshold voltage.
Claim 15
Dependent Claim
28 words
In the semiconductor integrated circuit device of claim 12 wherein the active pullup subcircuit comprises a MOSFET transistor connected between a voltage reference and the reduced voltage signal.
Claim 16
Dependent Claim
30 words
In the semiconductor integrated circuit device of claim 12 wherein the active pullup subcircuit comprises semiconductor diode means for unidirectionally conducting from a voltage reference to the reduced voltage signal.
Claim 17
Dependent Claim
37 words
In the semiconductor integrated circuit device of claim 12 wherein the active pullup subcircuit comprises a MOSFET transistor having a gate and drain connected to a voltage reference and a source connected to the reduced voltage signal.
Claim 18
Dependent Claim
28 words
In the semiconductor integrated circuit device of claim 1 wherein the active pullup subcircuit comprises a MOSFET transistor connected between a voltage reference and the reduced voltage signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-02 | 1995-12-02 | 1996-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-02 | 1999-12-02 | 2000-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-02 | 2003-12-02 | 2004-06-02 | $7700.00 | Window Closed / Lapsed |