Pipelined data processor with parameter files for passing parameters between pipeline units

Claim 1

Data processing apparatus comprising: a) an instruction scheduler for producing a sequence of instructions, b) an upper pipeline unit for generating operand addresses for each of said sequence of instructions, c) a data slave store for retrieving operands, specified by said operand addresses, d) a lower pipeline unit for performing operations on said operands, e) an instruction parameter file for passing the instruction from the instruction scheduler to the upper pipeline unit, the instruction parameter file comprising a plurality of independently addressable registers, f) an address parameter file for passing the operand addresses from the upper pipeline unit to the data slave store, the address parameter file comprising a plurality of independently addressable registers, g) an operand parameter file for passing the operands from the data slave store to the lower pipeline unit, the operand parameter file comprising a plurality of independently addressable registers, and, h) means operative whenever an instruction is scheduled by the instruction scheduler, for allocating one of said registers from the instruction parameter file to said instruction, and at the same time allocating one of said registers from the address parameter file and one of said registers from the operand parameter file to said instruction, and for deallocating said registers when said instruction is successfully completed by said lower pipeline unit.