Patent US5117487A successfully refreshed from Google Patents.
US5117487A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for accessing microprocessor and microinstruction control type microprocessor including pointer register
Assignee: Toshiba Corp
•
Filing: 1989-08-25
•
Granted: 1992-05-26
•
Expires: 2009-08-25
Abstract
Abstract In a microprocessor, a microinstruction is used to control the microprocessor. The microprocessor includes: a decoder for decoding the STC instruction to obtain a decoded instruction and address data, the address data designating an address of a control space allocated to a plurality of registers in a general-purpose register group; an address register for temporarily storing the address data derived from the decoder; a microinstruction storage unit for previously storing a plurality of microinstructions and for outputting the microinstruction one by one in response to the decoded instruction; a microinstruction register for producing a control signal in response to the read microinstruction; a calculation unit for calculating the address data sotred in the address register means to obtain bit information of the address data for designating a specific register in response to the bit information derived from the calculation unit, while the general-purpose register group; and, a pointer register for temporarily storing the bit information to access the specific register in response to the bit information derived from the calculation unit, while the general-purpose register group is instructed in response to the control signal.
Inventors
- 👤 Miyuki Nagata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:56
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
166 words
A microinstruction control type microprocessor comprising: decoder means for decoding an instruction to obtain a decoded instruction and address data; said address data designating an address of a control space allocated to a plurality of registers in a general-purpose register group; address register means for temporarily storing the address data derived from the decoder means; means for previously storing a plurality of microinstructions and for outputting said microinstructions one by one in response to the decoded instruction; means for temporarily storing said output microinstruction and for producing a control signal; calculation means for calculating the address data stored in the address register means to obtain bit information of the address data by shifting a preselected number of bits constituting said address data; and, pointer register means for temporarily storing the bit information derived from said calculation means, said bit information being used to access a specific register contained in said general-purpose register group, while the general-purpose register group is instructed in response to the control signal.
Claim 2
Dependent Claim
166 words
A microinstruction control type microprocessor comprising: decoder means for decoding an instruction to obtain a decoded instruction and address data; said address data designating an address of a control space allocated to a plurality of registers in a general-purpose register group; address register means for temporarily storing the address data derived from the decoder means; means for previously storing a plurality of microinstructions and for outputting said microinstructions one by one in response to the decoded instruction; means for temporarily storing said output microinstruction and for producing a control signal; calculation means for calculating the address data stored in the address register means to obtain bit information of the address data by shifting a preselected number of bits constituting said address data; and, pointer register means for temporarily storing the bit information derived from said calculation means, said bit information being used to access a specific register contained in said general-purpose register group, while the general-purpose register group is instructed in response to the control signal.
Claim 3
Dependent Claim
35 words
A microinstruction control type microprocessor as claimed in claim 1, wherein said microinstruction storing means includes a microinstruction storage unit, and a microinstruction register having a control field, a selection field, and an instruction field.
Claim 4
Dependent Claim
104 words
A microinstruction controlled type microprocessor as claimed in claim 1, further comprising: a first gate interposed between the pointer register means and general-purpose register group, for gating a supply of the bit information of the address data from the pointer register means to the general-purpose register group in response to a selection signal from the selection field of the microinstruction register; and, a second gate connected to an output of the general-purpose register group, for gating a supply of a content of the register accessed by the pointer register means in response to a control signal of the control field of the microinstruction register.
Claim 5
Dependent Claim
28 words
A microinstruction control type microprocessor as claimed in claim 1, further comprising: operand registers for storing operands contained in the address data supplied from the address register means.
Claim 6
Dependent Claim
27 words
A microinstruction control type microprocessor as claimed in claim 1, wherein said control space is used in a TRON (The Real-Time Operating System Nucleus) computer operating system.
Claim 7
Dependent Claim
66 words
A microinstruction control type microprocessor as claimed in claim 1, wherein said calculating means first shifts the address data by 3 bits from a least significant bit thereof, and secondly derives 4 bits of the bit-shifted address data from a new least significant bit of the bit-shifted address data, said 4 bits corresponding to the bit information of the address data for designating the specific register.
Claim 8
Independent Claim
137 words
A method for accessing a microinstruction control type microprocessor, comprising the steps of: decoding an instruction to obtain a decoded instruction and address data, said address data designating an address of a control space allocated to a plurality of registers in a general-purpose register group; storing said address data in an address register; reading a microinstruction in response to the decoded instruction from a microinstruction storage unit; producing a control signal in response to the microinstruction from a microinstruction register; calculating said address data so as to product bit information of the address data by shifting a preselected number of bits constituting said address data; and, accessing a specific register contained in said general-purpose register group based on said bit information of the address data, while instructing said general-purpose register group in response to said control signal.
Claim 9
Independent Claim
137 words
A method for accessing a microinstruction control type microprocessor, comprising the steps of: decoding an instruction to obtain a decoded instruction and address data, said address data designating an address of a control space allocated to a plurality of registers in a general-purpose register group; storing said address data in an address register; reading a microinstruction in response to the decoded instruction from a microinstruction storage unit; producing a control signal in response to the microinstruction from a microinstruction register; calculating said address data so as to product bit information of the address data by shifting a preselected number of bits constituting said address data; and, accessing a specific register contained in said general-purpose register group based on said bit information of the address data, while instructing said general-purpose register group in response to said control signal.
Claim 10
Dependent Claim
26 words
A method for accessing a microinstruction control type microprocessor as claimed in claim 7, wherein said register accessing operation is carried out by a pointer register.
Claim 11
Dependent Claim
60 words
A method for accessing a microinstruction control type microprocessor as claimed in claim 7, wherein said address data is first shifted by 3 bits from a least significant bit thereof, and secondly 4 bits of the bit-shifted address data are derived, said 4 bits address data corresponding to the bit information of the address data for designating the specific register.
Claim 12
Dependent Claim
27 words
A method for accessing a microinstruction control type microprocessor as claimed in claim 7, wherein said register accessing operation is executed in a TRON computer operating system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |