Packet switch for a transfer of data in asynchronous mode in a digital transmission network

Claim 1

In a digital transmission network, a packet switch for transferring, in an asynchronous mode, data from N incoming trunk lines to N outgoing trunk lines, each of said trunk lines having a respective input clock signal associated therewith, the switch comprising: an input adapting circuit, connected to the N incoming trunk lines, for converting series data, carried by the N incoming trunk lines at a rate of about 150 Mbits/s, into parallel data of n-bit packets and for producing a first memory stack clock signal for each of said n-bit packets; N input shift memory stacks, respectively associated with the N incoming trunk lines, having parallel inputs connected to corresponding outputs of the input adapting circuit and outputs for outputting stored data in packets of n times M bits, wherein M is a whole number, and using respective ones of said first memory stack clock signals; a multiplexer circuit for successively outputting the stored data, from each of the N input shift memory stacks, in packets of n times M bits; a single transfer bus for transferring all data transferred by the switch and for receiving the data outputted by the multiplexer in packets of n times M bits; N output shift memory stacks respectively connected to the single transfer bus, each having a n-bit parallel output; and an output adapting circuit connected to the outputs of the N output shift memories for converting parallel data received from the N output shirt memories to series data and for transferring the series data to the N outgoing trunk lines; wherein said output adapting circuit receives a respective output clock used for said transferring of said series data and produces a second memory stack clock signal for a respective one of said N output shift memories; wherein the input and output adapting circuits are one of an emitter coupled logic and a bipolar complementary metal oxide semiconductor integrated circuit which operate at a rate of about 150 Mhz; and wherein the input and output shift memory stacks are complementary metal oxide semiconductor circuits which operate at a rate of about 20 MHz.