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Patent US5115149A successfully refreshed from Google Patents.
US5115149A
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US
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Bidirectional I/O signal separation circuit
Assignee: Sharp Corp
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Filing: 1991-03-28
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Granted: 1992-05-19
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Expires: 2011-03-28
Abstract
Abstract A bidirectional I/O signal separation circuit for connecting a circuit device having a bidirectional I/O terminal with another circuit device having individual input and output terminals, in which an output signal of the circuit device to be connected is not supplied to an input terminal of the same circuit device, and which is able to establish a connection between a semiconductor IC device in which the logical level of a signal is used as information and a semiconductor IC device in which a pulse signal is used as information.
Inventors
- 👤 Yoshinori Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:20
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/14; H04L5/16; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
315 words
A bidirectional I/O signal separation circuit for connecting a first circuit device having a bidirectional I/O terminal with a second circuit device having individual input and output terminals, said bidirectional I/O signal separation circuit comprising: an output control circuit connected to said output terminal for generating an output control pulse signal when a logical level of a signal transmitted from said output terminal is changed; an input control circuit connected to said output terminal for generating an input control pulse signal when said logical level of said signal transmitted from said output terminal is changed; an output signal generating circuit connected to said output terminal for generating an output pulse signal when said logical level of said signal transmitted from said output terminal is changed; a buffer circuit having an input connected to said output signal generating circuit and an output connected to said I/O terminal and adapted to permit said output pulse signal to be supplied to said I/O terminal during a period of time during which said output control pulse signal is supplied to a control terminal thereof and brings said output thereof into a high impedance state during a period of time during which said output control pulse signal is not supplied to said control terminal; a gate circuit having an input connected to said I/O terminal and adapted to block a pulse signal transmitted from said I/O terminal during a period of time during which said input control pulse signal is supplied to a control terminal thereof; and an input signal generating circuit having an input connected to an output of said gate circuit and an output connected to said input terminal and adapted to generate a signal whose logical level is changed whenever said input signal generating circuit receives, via said gate circuit, said pulse signal transmitted from said I/O terminal and supply said generated signal to said input terminal.
Claim 2
Dependent Claim
315 words
A bidirectional I/O signal separation circuit for connecting a first circuit device having a bidirectional I/O terminal with a second circuit device having individual input and output terminals, said bidirectional I/O signal separation circuit comprising: an output control circuit connected to said output terminal for generating an output control pulse signal when a logical level of a signal transmitted from said output terminal is changed; an input control circuit connected to said output terminal for generating an input control pulse signal when said logical level of said signal transmitted from said output terminal is changed; an output signal generating circuit connected to said output terminal for generating an output pulse signal when said logical level of said signal transmitted from said output terminal is changed; a buffer circuit having an input connected to said output signal generating circuit and an output connected to said I/O terminal and adapted to permit said output pulse signal to be supplied to said I/O terminal during a period of time during which said output control pulse signal is supplied to a control terminal thereof and brings said output thereof into a high impedance state during a period of time during which said output control pulse signal is not supplied to said control terminal; a gate circuit having an input connected to said I/O terminal and adapted to block a pulse signal transmitted from said I/O terminal during a period of time during which said input control pulse signal is supplied to a control terminal thereof; and an input signal generating circuit having an input connected to an output of said gate circuit and an output connected to said input terminal and adapted to generate a signal whose logical level is changed whenever said input signal generating circuit receives, via said gate circuit, said pulse signal transmitted from said I/O terminal and supply said generated signal to said input terminal.
Claim 3
Dependent Claim
29 words
A bidirectional I/O signal separation circuit according to claim 1, wherein each of said first and second circuit devices is a semiconductor IC formed on a single semiconductor substrate.
Claim 4
Dependent Claim
353 words
A bidirectional I/O signal separation circuit for connecting a first circuit device having a bidirectional I/O terminal with a second circuit device having individual input and output terminals, said bidirectional I/O signal separation circuit comprising: an output control circuit connected to said output terminal for generating an output control pulse signal when a logical level of a signal transmitted from said output terminal is changed; an input control circuit connected to said output terminal for generating an input control pulse signal when said logical level of said signal transmitted from said output terminal is changed; an output signal generating circuit connected to said output terminal for generating an output pulse signal when said logical level of said signal transmitted from said output terminal is changed; a buffer circuit having an input connected to said output signal generating circuit and an output connected to said I/O terminal and adapted to permit said output pulse signal to be supplied to said I/O terminal during a period of time during which said output control pulse signal is supplied to a control terminal thereof and brings said output thereof into a high impedance state during a period of time during which said output control pulse signal is not supplied to said control terminal; a gate circuit having an input connected to said I/O terminal and adapted to block a pulse signal transmitted from said I/O terminal during a period of time during which said input control pulse signal is supplied to a control terminal thereof; and an input signal generating circuit having an input connected to an output of said gate circuit and an output connected to said input terminal and adapted to generate a signal of first logical level on receiving, via said gate circuit, said pulse signal transmitted from said I/O terminal at said input thereof and supply said generated signal of said first logical level to said input terminal, and to generate a signal of second logical level on receiving said output control pulse signal at a control terminal thereof and supply said generated signal of said second logical level to said input terminal.
Claim 5
Dependent Claim
353 words
A bidirectional I/O signal separation circuit for connecting a first circuit device having a bidirectional I/O terminal with a second circuit device having individual input and output terminals, said bidirectional I/O signal separation circuit comprising: an output control circuit connected to said output terminal for generating an output control pulse signal when a logical level of a signal transmitted from said output terminal is changed; an input control circuit connected to said output terminal for generating an input control pulse signal when said logical level of said signal transmitted from said output terminal is changed; an output signal generating circuit connected to said output terminal for generating an output pulse signal when said logical level of said signal transmitted from said output terminal is changed; a buffer circuit having an input connected to said output signal generating circuit and an output connected to said I/O terminal and adapted to permit said output pulse signal to be supplied to said I/O terminal during a period of time during which said output control pulse signal is supplied to a control terminal thereof and brings said output thereof into a high impedance state during a period of time during which said output control pulse signal is not supplied to said control terminal; a gate circuit having an input connected to said I/O terminal and adapted to block a pulse signal transmitted from said I/O terminal during a period of time during which said input control pulse signal is supplied to a control terminal thereof; and an input signal generating circuit having an input connected to an output of said gate circuit and an output connected to said input terminal and adapted to generate a signal of first logical level on receiving, via said gate circuit, said pulse signal transmitted from said I/O terminal at said input thereof and supply said generated signal of said first logical level to said input terminal, and to generate a signal of second logical level on receiving said output control pulse signal at a control terminal thereof and supply said generated signal of said second logical level to said input terminal.
Claim 6
Dependent Claim
29 words
A bidirectional I/O signal separation circuit according to claim 3, wherein each of said first and second circuit devices is a semiconductor IC formed on a single semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |