Frequency-dividing circuit

Claim 2

A frequency-dividing circuit comprising: a latch circuit (20) having a first and second complementary terminals (N21, N22); first and second amplify/delay circuits (31, 32) each having an input and an output, each of said first and second amplify/delay circuits comprising a cascade coupling of an amplifying inverter and a delay circuit, said amplifying inverter being arranged to drive said latched circuit; and first and second switches (11, 12) each having a respective control electrode, said control electrodes being coupled to receive an input signal (CK, N42) alternately assuming a first state or a second state, each of said switches so connected as to be simultaneously conductive when said input signal is in said first state and simultaneously nonconductive when said input signal is in said second state, each said switch coupling an output from a respective one of said amplify/delay circuits to a respective one of said complementary terminals and to an input of said the amplify/delay circuit.

Claim 3

A frequency-dividing circuit according to claim 1, wherein each of said switches (11, 12) comprises a field-effect transistor having first and second main electrodes and being turned on and off across the first and second main electrodes by the control signal applied to the control electrode; said first complementary terminal (N21) is connected to said second main electrode of the transistor forming said second switch (12); said second complementary terminal (N22) is connected to said second main electrode of the transistor forming said first switch (11); and each of said first main electrodes is coupled to receive a respective predetermined output selected from the first amplify/delay circuit and the second amplify/delay circuit.

Claim 4

A frequency-dividing circuit according to claim 1, wherein a frequency-divided output is derived at at least one of the outputs of said first and second amplify/delay circuits (31, 32).

Claim 5

A frequency-dividing circuit according to claim 1, wherein each of the first and second amplify/delay circuits (31, 32) is formed of an even number of cascaded inverters, said first complementary terminal (N21) of said latch circuit (20) is connected to receive the output of said first amplify/delay circuit (31), via said second switch, and said complementary terminal (N22) of said latch circuit (20) is connected to receive the output of said second amplify/delay circuit (32) via said first switch.

Claim 6

A frequency-dividing circuit according to claim 1, wherein each of the first and second amplify/delay circuits (31, 32) is formed of an odd number of inverters, said first complementary terminal (N21) of said latch circuit (20) is connected to receive the output of said second amplify/delay circuit (32) via said second switch, and said second complementary terminal (N22) of said latch circuit (20) is connected to receive the output of said first amplify/delay circuit via said first switch (31).

Claim 7

A frequency-dividing circuit according claim 1, wherein said latch circuit (20) comprises a first and second inverting circuits (21, 22); said first inverting circuit (21) has an output terminal connected to said first complementary terminal (N21) and an input terminal connected to said second complementary terminal (N22); said second inverting circuit (22) has an output terminal connected to said second complementary terminal (N22) and an input terminal connected to said first complementary terminal (N21); and each of said first and second inverting circuits (21, 22) outputs a signal which is an inversion of a signal applied to the input terminal.

Claim 8

A frequency-dividing circuit according to claim 6, wherein at least one of said first and second inverting circuits (21, 22) comprises an inverter having an input and output respectively constituting the input and output of the inverting circuit.

Claim 9

A frequency-dividing circuit according to claim 6, wherein at least one of said first and second inverting circuits (21, 22) comprises a NOR gate having a first input and an output respectively constituting the input and output of the inverting circuit, and having a second input receiving a control signal for resetting the frequency-dividing circuit.

Claim 10

A frequency-dividing circuit according to claim 7, wherein at least one of said first and second inverting circuits (2-, 22) comprises a NAND gate having a first input and an output respectively constituting the input and output of the inverting circuit, and having a second input receiving a control signal for resetting the frequency-dividing circuit.

Claim 11

A frequency-dividing circuit according to claim 1, wherein the time for which the input signal (CK) is at a level for turning on the switches (11, 12) is shorter than a delay time from the output of one of said amplify/delay circuits (31 or 32) through one of said switches (11, 12) and the other amplify/delay circuit (32 or 31) to the output of said other amplify/delay circuit (32 or 31), and the period of the input signal is longer than said delay time.

Claim 12

A frequency-dividing circuit according to claim 1, further comprising means for reducing the interval for which the input signal assumes said first state.

Claim 13

A frequency-dividing circuit according to claim 11, wherein said means for reducing the interval comprises an inverter receiving an input signal, and a NOR gate receiving the output of the inverter and said input signal, and the output of the NOR gate is applied to the control electrodes of the switches.

Claim 14

A frequency-dividing circuit comprising: a latch circuit (20) having a first and second complementary terminals (N21, N22), said latch circuit comprising a first and second inverting circuits (21, 22), said first inverting circuit having an output terminal connected to said first complementary terminal (N21) and an input terminal connected to said second complementary terminal (N22), said second inverting circuit having an output terminal connected to said second complementary terminal (N22) and an input terminal connected to said first complementary terminal (N21), each of said first and second inverting circuits outputting a signal which is an inversion of a signal applied to the input terminal; first and second amplify/delay circuits (31, 32) for delaying signals applied to respective inputs thereof, each of said first and second amplify/delay circuits comprising a cascade coupling of an amplifying inverter and a delay circuit, said amplifying inverter being arranged to drive said latch circuit; first and second field-effect transistors (11, 12) each having first and second main electrodes and a control electrode connected to receive an input signal (CK, N42) alternately assuming a first state or a second state, each of said transistors being so connected as to be simultaneously conductive across their first and second main electrodes when said input signal is in said first state, and simultaneously nonconductive when said input signal is in second state; wherein said first complementary terminal (N21) is connected to said second main electrode of said second transistor (12) and the input of said second amplify/delay circuit (32); said second complementary terminal (N22) is connected to said second main electrode of said first transistor (11) and the input of said first amplify/delay circuit (31); and each said transistor coupling an output from a respective one of said amplify/delay circuit to a respective on of said complementary terminals.

Claim 15

A frequency-dividing circuit comprising: a latch circuit (20) having a first and second complementary terminals (N21, N22), said latch circuit comprising a first and second inverting circuits (21, 22), said first inverting circuit having an output terminal connected to said first complementary terminal (N21) and an input terminal connected to said second complementary terminal (N22), said second inverting circuit having an output terminal connected to said second complementary terminal (N22) and an input terminal connected to said first complementary terminal (N21), each of said first and second inverting circuits outputting a signal which is an inversion of a signal applied to the input terminal; first and second amplify/delay circuits (31, 32) for delaying signals applied to respective inputs thereof, each of said first and second amplify/delay circuits comprising a cascade coupling of an amplifying inverter and a delay circuit, said amplifying inverter being arranged to drive said latch circuit; first and second field-effect transistors (11, 12) each having first and second main electrodes and a control electrode connected to receive an input signal (CK, N42) alternately assuming a first state or a second state, each of said transistors being so connected as to be simultaneously conductive across their first and second main electrodes when said input signal is in said first state, and simultaneously nonconductive when said input signal is in second state; wherein said first complementary terminal (N21) is connected to said second main electrode of said second transistor (12) and the input of said second amplify/delay circuit (32); said second complementary terminal (N22) is connected to said second main electrode of said first transistor (11) and the input of said first amplify/delay circuit (31); and each said transistor coupling an output from a respective one of said amplify/delay circuit to a respective on of said complementary terminals.

Claim 16

A frequency-dividing circuit according to claim 13, wherein a frequency-divided output is derived at at least one of the outputs of said first and second amplify/delay circuits (31, 32).

Claim 17

A frequency-dividing circuit comprising: a latch circuit having a first and second complementary terminals (N21, N22); first and second amplify/delay circuits (31, 32) for delaying signals applied to respective inputs thereof; each of said first and second amplify/delay circuits comprising a cascade coupling of an amplifying inverter and a delay circuit, said amplifying inverters being arranged to drive said latch circuit; each of the first and second amplify/delay circuits producing an output which is nearly in phase but delayed with respect to its input; first and second switches (11, 12) each having a control electrode connected to receive an input signal (CK, N42) alternately assuming a first state or a second state, each of said switches so connected as to be simultaneously conductive when said input signal is in said first state and simultaneously nonconductive when said input signal is in said second state; wherein said first complementary terminal (N21) is connected to the input of said second amplify/delay circuit (32) and connected to receive through said second switch (12) the output of said first amplify/delay circuit (31); and said second complementary terminal (N22) is connected to the input of said first amplify/delay circuit (31) and connected to receive through said first switch (11) the output of said second amplify/delay circuit (32).

Claim 18

A frequency-dividing circuit comprising: a latch circuit having a first and second complementary terminals (N21, N22); first and second amplify/delay circuits (31, 32) for delaying signals applied to respective inputs thereof; each of said first and second amplify/delay circuits comprising a cascade coupling of an amplifying inverter and a delay circuit, said amplifying inverters being arranged to drive said latch circuit; each of the first and second amplify/delay circuits producing an output which is nearly in phase but delayed with respect to its input; first and second switches (11, 12) each having a control electrode connected to receive an input signal (CK, N42) alternately assuming a first state or a second state, each of said switches so connected as to be simultaneously conductive when said input signal is in said first state and simultaneously nonconductive when said input signal is in said second state; wherein said first complementary terminal (N21) is connected to the input of said second amplify/delay circuit (32) and connected to receive through said second switch (12) the output of said first amplify/delay circuit (31); and said second complementary terminal (N22) is connected to the input of said first amplify/delay circuit (31) and connected to receive through said first switch (11) the output of said second amplify/delay circuit (32).

Claim 19

A frequency-dividing circuit according to claim 15, wherein each of said first and second amplify/delay circuits (31, 32) is formed of a cascade coupling of an even number of inverters.

Claim 20

A frequency-dividing circuit comprising: a latch circuit having a first and second complementary terminals (N21, N22); first and second amplify/delay circuits (31, 32) for delaying signals applied to respective inputs thereof; each of said first and second amplify/delay circuits comprising a cascade coupling of an amplifying inverter and a delay circuit, said amplifying inverters being arranged to drive said latch circuit; each of the first and second amplify/delay circuits producing an output which is nearly an inversion of and delayed with respect to its input; first and second switches (11, 12) each having a controlled electrode connected to receive an input signal (CK, N42) alternately assuming a first state or a second state, each of said switches so connected as to be simultaneously conductive when said input signal is in said first state and simultaneously nonconductive when said input signal is in said second stage; wherein said first complementary terminal (N21) is connected to the input of said second amplify/delay circuit (32) and connected to receive through said second switch (12) the output of said second amplify/delay circuit (32); and said complementary terminal (N22) is connected to the input of said first amplify/delay circuit (31) and connected to receive through said first switch (11) the output of said first amplify/delay circuit (31).

Claim 21

A frequency-dividing circuit comprising: a latch circuit having a first and second complementary terminals (N21, N22); first and second amplify/delay circuits (31, 32) for delaying signals applied to respective inputs thereof; each of said first and second amplify/delay circuits comprising a cascade coupling of an amplifying inverter and a delay circuit, said amplifying inverters being arranged to drive said latch circuit; each of the first and second amplify/delay circuits producing an output which is nearly an inversion of and delayed with respect to its input; first and second switches (11, 12) each having a controlled electrode connected to receive an input signal (CK, N42) alternately assuming a first state or a second state, each of said switches so connected as to be simultaneously conductive when said input signal is in said first state and simultaneously nonconductive when said input signal is in said second stage; wherein said first complementary terminal (N21) is connected to the input of said second amplify/delay circuit (32) and connected to receive through said second switch (12) the output of said second amplify/delay circuit (32); and said complementary terminal (N22) is connected to the input of said first amplify/delay circuit (31) and connected to receive through said first switch (11) the output of said first amplify/delay circuit (31).

Claim 22

A frequency-dividing circuit according to claim 17, wherein each of said amplify/delay circuits is formed of a cascade coupling of an odd number of inverters.