Asynchronous leading zero counter employing iterative cellular array

Claim 2

Leading zero detector comprising a cell including asynchronous logic circuitry having a pair of digital data inputs and a data output for providing an indication that a leading zero has been detected on the digital data inputs including a count of the number of leading zeros detected on the data inputs, the cell being cascadable with a selectable number of other like cells to incrementally increase a maximum count of the numbers of detected leading zeros.

Claim 3

Leading zero detector according to claim 1 wherein the asynchronous logic circuitry further has an enable/disable input and a carry input, the asynchronous logic circuitry rendering the data output responsive to only the carry input when the cell is disabled, but rendering the data output active upon detecting a binary 01 at the data inputs when the cell is enabled.

Claim 4

Leading zero detector according to claim 2 wherein the asynchronous logic circuit renders the data output inactive when both the cell is enabled and a binary 10 or 11 is detected at the data inputs.

Claim 5

Leading zero detector according to claim 4 further comprising an enable output from the asynchronous logic circuit, the asynchronous logic circuit rendering the enable output active when both the cell is enabled and a binary 00 is detected at the data inputs.

Claim 6

Leading zero detector according to claim 4 wherein, the cell is one of a plurality of cells cascaded in an array, and the array comprises a number of cells defining a first row having the data inputs coupled to sequential bits of a bus, and at least one succeeding row of cells, each succeeding row of cells having half the number of cells than the immediately preceding row, each cell except a first cell in each row having its data output coupled to the carry input of a next immediately neighboring cell in the same row, each cell in each of the succeeding rows having its data inputs coupled to the enable outputs of a pair of adjacent cells in the immediately preceding row, the data output of the first cell in each row collectively providing a digital word having a magnitude indicative of the number of leading zeros on the bus.

Claim 7

Leading zero detector array according to claim 5 wherein there is no crossover of any signal lines interconnecting the cells.

Claim 8

Leading zero detector array according to claim 5 wherein the bus has 2 N bits, and there are N-1 cells defining N rows.

Claim 9

Leading zero detector array according to claim 5 wherein the enable output of a last cell in the array is active when binary 0's are present on all data inputs of the first row of cells, and is inactive at all other times.

Claim 10

Leading zero counter cell comprising: (a) a first data input (In0) to an asynchronous logic circuit for receiving a signal indicative of the status of a bit; (b) a second data input (In1) to the asynchronous logic circuit for receiving another signal indicative of the status of an immediately preceding less significant bit; (c) an enable input (G) to the asynchronous logic circuit for enabling/disabling the cell; (d) a carry input (Yin) to the asynchronous logic circuit; (e) a first output (Y) from the asynchronous logic circuit for providing an indication of leading zero count on the first and second data inputs (In0, In1), the first output (Y) being responsive only to the status of the carry input (Yin) when the cell is disabled but being responsive to the status of the first and second data inputs (In0, In1) when the cell is enabled; and, (f) a second output (In=0) from the asynchronous logic circuit for providing a first indication that both (i) the cell is enabled and (ii) the signals received on the first and second data inputs (In0, In1) both indicate binary 0, but otherwise providing a second opposite indication; the cell being cascadable with a selectable number of other like cells to incrementally increase a maximum count of the number of detected heading zeros.

Claim 11

Leading zero counter cell comprising: (a) a first data input (In0) to an asynchronous logic circuit for receiving a signal indicative of the status of a bit; (b) a second data input (In1) to the asynchronous logic circuit for receiving another signal indicative of the status of an immediately preceding less significant bit; (c) an enable input (G) to the asynchronous logic circuit for enabling/disabling the cell; (d) a carry input (Yin) to the asynchronous logic circuit; (e) a first output (Y) from the asynchronous logic circuit for providing an indication of leading zero count on the first and second data inputs (In0, In1), the first output (Y) being responsive only to the status of the carry input (Yin) when the cell is disabled but being responsive to the status of the first and second data inputs (In0, In1) when the cell is enabled; and, (f) a second output (In=0) from the asynchronous logic circuit for providing a first indication that both (i) the cell is enabled and (ii) the signals received on the first and second data inputs (In0, In1) both indicate binary 0, but otherwise providing a second opposite indication; the cell being cascadable with a selectable number of other like cells to incrementally increase a maximum count of the number of detected heading zeros.

Claim 12

Leading zero counter cell according to claim 9 whereupon, when the signal received on the In0 input indicates a binary 1, the In=0 output provides the second indication and the Y output provides an indication that the leading zero count is zero.

Claim 13

Leading zero counter cell according to claim 9 wherein the Y and In=0 outputs are responsive to the In0, In1, Yin and G inputs according to the following truth table: ______________________________________ G Yin In0 Inl Y In=0 ______________________________________ l 0 x x 0 1 l l x x l 1 0 0 0 0 0 0 0 0 0 l 1 l 0 0 l x 0 l ______________________________________ where x is a "don't care."

Claim 14

Leading zero counter cell according to claim 9 wherein the asynchronous logic circuit comprises: a first AND gate having inverted inputs receiving the G and In0 inputs to the cell and a non-inverted input receiving the In1 input to the cell; a second AND gate having inverted inputs receiving the G, In0 and In1 inputs to the cell and having an inverted output providing the In=0 output from the cell; and, an OR gate having inputs receiving the Yin input to the cell and an output of the first AND gate, and having an output for providing the Y output from the cell.

Claim 15

Leading zero counter cell according to claim 9 wherein the In0, In1 and Yin inputs are active high inputs, the G input is an active low input, the Y output is an active high output and the In=0 output is an active low output.

Claim 16

Leading zero counter cell according to claim 9 wherein the cell is one of a plurality of cells interconnected in an array.

Claim 17

Leading zero counter cell array according to claim 14 wherein the array is defined by at least one row, a first cell in the row being associated with two least significant bits of a bus, a last cell being associated with two most significant bits of the bus, and the remaining cells being associated, in succession, with bit pairs of the bus therebetween, and the Y output and In=0 output of all except the first cell being coupled to the Yin input and G input, respectively, of an immediately neighboring cell that is associated with two lower significant bits of the bus, the Y output of the first cell being indicative of the least significant bit of the leading zero count.

Claim 18

Leading zero counter cell array according to claim 15 wherein there are 2 N bits in the bus, the array is two dimensional and the recited row defines a first row, there being a total of N rows of cells in the array including at least one row succeeding the first row, each row succeeding the first row containing only half of the number of cells of the immediately preceding row, the Y output of a first cell of each row succeeding the first row being indicative of a higher significant bit of the leading zero count.

Claim 19

Leading zero counter cell array according to claim 16 wherein the In0 and In1 inputs of each cell in the rows succeeding the first row are coupled to receive the In=0 outputs of a pair of cells in the immediately preceding row.

Claim 20

Leading zero counter cell array according to claim 16 wherein the number of cells in the array is 2 N -1.

Claim 21

Leading zero counter cell array according to claim 16 wherein the Y outputs of the first cell of each row collectively provide a digital word having a magnitude indicative of the leading zero count on the bus.

Claim 22

Leading zero counter cell array according to claim 19 wherein the array operation is parallel and asynchronous.

Claim 23

Leading zero counter cell array according to claim 16 wherein the In=0 output of at last cell in the array provides the first indication when binary 0's are present on all In0 and In1 inputs of the first row of cells, and provides the second indication at all other times.

Claim 24

Leading zero counter cell array according to claim 14 wherein there is no crossover of signal lines interconnecting the cells of the array.

Claim 25

Apparatus for providing an indication of leading zero count on a 2 N bit bus comprising a plurality, 2 N -1, of cascaded asynchronous zero detector cells defining N rows, a first row being defined by a number 2 N /2 of zero detector cells coupled to receive all of the bits of the bus and provide an output indicative of a least significant bit of the leading zero count, each succeeding row being defined by half of the number of zero detectors in the immediately preceding row, each zero detector cell in each succeeding row being coupled to receive an output of a pair of zero detectors in the immediately preceding row, each succeeding row providing an output indicative of a more significant bit of the leading zero count, the outputs from the N rows collectively defining a digital word having a magnitude indicative of the leading zero count.

Claim 26

Apparatus for providing an indication of leading zero count on a 2 N bit bus comprising a plurality, 2 N -1, of cascaded asynchronous zero detector cells defining N rows, a first row being defined by a number 2 N /2 of zero detector cells coupled to receive all of the bits of the bus and provide an output indicative of a least significant bit of the leading zero count, each succeeding row being defined by half of the number of zero detectors in the immediately preceding row, each zero detector cell in each succeeding row being coupled to receive an output of a pair of zero detectors in the immediately preceding row, each succeeding row providing an output indicative of a more significant bit of the leading zero count, the outputs from the N rows collectively defining a digital word having a magnitude indicative of the leading zero count.

Claim 27

Apparatus according to claim 23 there is no crossover of signal lines interconnecting the cells.

Claim 28

Apparatus according to claim 23 wherein each zero detector cell comprises: (a) a first data input (In0) for receiving a signal indicative of the status of a bit, the first data input (In0) of each cell in the first row being coupled to receive a bit of the bus; (b) a second data input (In1) for receiving another signal indicative of the status of a neighboring bit, the second data input (In1) of each cell in the first row being coupled to receive an immediately preceding less significant bit of the bus than the first data input (In0); (c) an enable input (G) for enabling/disabling the cell; (d) a carry input (Yin); (e) a first output (Y) for providing an indication of leading zero count on the first and second data inputs (In0, In1), the first output (Y) being responsive only to the status of the carry input (Yin) when the cell is disabled but being responsive to the status of the first and second data inputs (In0, In1) when the cell is enabled; and, (f) a second output (In=0) for providing a first indication that both (i) the cell is enabled and (ii) the signals received on the first and second data inputs (In0, In1) both indicate binary 0, but otherwise providing a second opposite indication.

Claim 29

Apparatus according to claim 25 wherein the Y and In=0 outputs are responsive to the In0, In1, Yin and G inputs according to the following truth table: ______________________________________ G Yin In0 Inl Y In=0 ______________________________________ 1 0 x x 0 l l 1 x x l 1 0 0 0 0 0 0 0 0 0 l l l 0 0 1 x 0 l ______________________________________ where x is a "don't care."

Claim 30

Apparatus according to claim 26 wherein the In0 and In1 inputs of each cell in the rows succeeding the first row are coupled to receive the In=0 outputs of a pair of cells in the immediately preceding row.

Claim 31

Apparatus according to claim 25 wherein the In=0 output of a last cell in the array provides the first indication when binary 0's are present on all In0 and In1 inputs of the first row of cells, and provides the second indication at all other times.

Claim 32

Asynchronous leading zero counter for a bus comprising a plurality of cascaded zero detector cells arranged in an array, each zero detector cell having first and second data inputs (In0,In1), and a primary functional output (Y), a plurality of the cells defining a first row of the array and each having its In0 input coupled to receive one bit of the bus and its In1 input coupled to receive an immediately preceding less significant bit of the bus, a first of the cells of the first row being associated with two least significant bits of the bus, a last of the cells of the first row being associated with two most significant bits of the bus, and the remaining cells being associated, in succession, with bit pairs of the bus therebetween, the Y output of the first cell of the first row providing an output indicative of a least significant bit of the leading zero count, a plurality of additional cells defining succeeding rows, each succeeding row being defined by half the number of cells in the immediately preceding row, the In0 and In1 inputs of each cell in each succeeding row being coupled to receive outputs of a pair of cells in the immediately preceding row, the Y output of the first cell of each succeeding row providing an output indicative of a more significant bit of the leading zero count, the Y outputs of the first cell of each row collectively providing a digital word having a magnitude indicative of leading zero count.

Claim 33

Asynchronous leading zero counter for a bus comprising a plurality of cascaded zero detector cells arranged in an array, each zero detector cell having first and second data inputs (In0,In1), and a primary functional output (Y), a plurality of the cells defining a first row of the array and each having its In0 input coupled to receive one bit of the bus and its In1 input coupled to receive an immediately preceding less significant bit of the bus, a first of the cells of the first row being associated with two least significant bits of the bus, a last of the cells of the first row being associated with two most significant bits of the bus, and the remaining cells being associated, in succession, with bit pairs of the bus therebetween, the Y output of the first cell of the first row providing an output indicative of a least significant bit of the leading zero count, a plurality of additional cells defining succeeding rows, each succeeding row being defined by half the number of cells in the immediately preceding row, the In0 and In1 inputs of each cell in each succeeding row being coupled to receive outputs of a pair of cells in the immediately preceding row, the Y output of the first cell of each succeeding row providing an output indicative of a more significant bit of the leading zero count, the Y outputs of the first cell of each row collectively providing a digital word having a magnitude indicative of leading zero count.

Claim 34

Asynchronous leading zero counter according to claim 29 wherein each cell further comprises an enable input (G), a carry input (Yin) and an enable output (In=0), and the In0 and In1 inputs of each cell in each succeeding row are coupled to receive the In=0 outputs of adjacent pairs of cells in the immediately preceding row, and the Y output and In=0 output of each cell, except the first cell in each row, is coupled to the Yin input and G input, respectively, of an immediately neighboring cell in the row that is associated with two lower significant bits of the bus.

Claim 35

Asynchronous leading zero counter according to claim 30 wherein the Y output is responsive to only the Yin input when the G input disables the cell but is responsive to the In0 and In1 inputs when the G input enables the cell.

Claim 36

Asynchronous leading zero counter according to claim 31 wherein: (a) upon the presence of a binary 01 on the inputs In0, In1, respectively, of any of the cells, the Y outputs of all cells associated with less significant bits are forced to an active state and those cells are disabled; and, (b) upon the presence of a binary 1 on the input In0, the Y outputs of all cells associated with less significant bits are forced to an inactive state and those cells are disabled.

Claim 37

Asynchronous leading zero counter according to claim 30 wherein the enable output of a last cell in the array is active when binary 0's are present on all data inputs of the first row of cells, and is inactive at all other times.

Claim 38

Asynchronous leading zero counter according to claim 29 wherein there are 2 N bits in the bus, 2 N -1 cells and N rows of cells in the array.

Claim 39

Asynchronous leading zero counter according to claim 29 wherein there is no crossover of signal lines coupling the cells of the array.