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US5111034A
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Apparatus utilizing light emitting semiconductor device
Assignee: Omron Corp
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Filing: 1990-07-19
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Granted: 1992-05-05
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Expires: 2010-07-19
Abstract
Abstract Disclosed is an apparatus utilizing a light emitting semiconductor device which has a pumped region and an unpumped absorber region and in which an active layer has a quantum well structure. In this light emitting semiconductor device, driving current/light output characteristics have dependence on the pulse width of a driving current. A logic unit or a noise reducing apparatus is realized utilizing this property. Furthermore, in the above described light emitting semiconductor device, the central wavelength of emitted light has dependence on a driving current or dependence on driving time. A light beam scanner can be realized utilizing this property.
Inventors
- 👤 Takeshi Takagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:35
CPC Classifications
B; B82; B82Y; B82Y20/00; G; G02; G02F; G02F3/00; G02F3/02; G02F3/026; H; H01; H01S; H01S5/00; H01S5/04; H01S5/042; H01S5/0425; H01S5/04256; H01S5/06; H01S5/0601; H01S5/30; H01S5/34; H03; H03K; H03K19/00; H03K19/02; H03K19/14; H01S5/0602; H01S5/062; H01S5/06209; H01S5/06213; H01S5/0622; H01S5/06233; H01S5/06243; H01S5/10; H01S5/1039; H01S5/20; H01S5/22; H01S5/223; H01S5/2231; H10; H10H; H10H20/00; H10H20/80; H10H20/81; H10H20/811; H10H20/812; H10H20/822; H10H20/824
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
197 words
A logic unit comprising: at least two input means for respectively converting at least two logical electric signals into output signals having a predetermined pulse width depending on the logical values represented by the electric signals; delay means for delaying an output signal of one of the input means by time corresponding to the pulse width applied to an output signal of the other input means; a light emitting semiconductor device which has a pumped region and an unpumped absorber region and in which an active layer has a quantum well structure and driving current/light output characteristics have dependence on the pulse width of a driving current; means for adding an output signal of said delay means and the output signal of said other input means to drive said light emitting semiconductor device by the added output therefrom; a light receiving device for receiving light emitted from said light emitting semiconductor device to generate a light reception signal at a level corresponding to the amount of the received light; and level determining means for determining the light reception signal outputted from said light receiving device at a threshold level corresponding to the type of a logic operation.
Claim 2
Dependent Claim
197 words
A logic unit comprising: at least two input means for respectively converting at least two logical electric signals into output signals having a predetermined pulse width depending on the logical values represented by the electric signals; delay means for delaying an output signal of one of the input means by time corresponding to the pulse width applied to an output signal of the other input means; a light emitting semiconductor device which has a pumped region and an unpumped absorber region and in which an active layer has a quantum well structure and driving current/light output characteristics have dependence on the pulse width of a driving current; means for adding an output signal of said delay means and the output signal of said other input means to drive said light emitting semiconductor device by the added output therefrom; a light receiving device for receiving light emitted from said light emitting semiconductor device to generate a light reception signal at a level corresponding to the amount of the received light; and level determining means for determining the light reception signal outputted from said light receiving device at a threshold level corresponding to the type of a logic operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-05 | 1995-11-04 | 1996-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-05 | 1999-11-04 | 2000-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-05 | 2003-11-04 | 2004-05-05 | $7700.00 | Window Closed / Lapsed |