US5107263A
Expired / Lapsed
US
⏱️ 0.0 years remaining
NRZ to CMI (II) encoding circuit
Assignee: KOREA TELECOMMUNICATION AUTHORITY A CORP OF KOREA
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Filing: 1990-12-07
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Granted: 1992-04-21
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Expires: 2010-12-07
Abstract
Abstract A NRZ/CMI (II) code converter comprising a D-type flip-flop for retiming a series of NRZ data bits received thereto with a clock synchronized therewith, an OR-gate connected to said one output of the D-type flip-flop to compose space bits of a series of said received NRZ data bits and a transmitted clock, and a delay element connected to the output of said OR-gate. The converter also comprises another OR gate connected to a negative output of said D-type flip-flop and another D-type flip-flop having a clock input connected to the output of said OR-gate. These elements function to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits. An exclusive OR-gate is connected to the output of said another OR-gate and the output of said another D-type flip-flop. In the exclusive OR-gate, mark bits are alternatively generated at the mark bit portions of a series of the NRZ data bits, and clock pulses are composed with a series of the NRZ data bits at the space bit portions of a series of the NRZ data bits. In addition, mark bits and space bits of a series of the NRZ data bits can be independently processed for the same time, in order to generate the CMI (II) code.
Inventors
- 👤 Bong T. Kim
- 👤 Kwon C. Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:23
CPC Classifications
H; H03; H03M; H03M5/00; H03M5/02; H03M5/04; H03M5/06; H03M5/12; H03M5/14; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908; H04L25/491; H04L25/4912
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
211 words
A NRZ to CMI (II) encoding circuit comprising: retiming means for retiming a series of NRZ data bits received thereto with a clock synchronized therewith; space bits-generating and delaying means connected to an output of said retiming means to compose space bits of a series of said received NRZ data bits and a NRZ data transmitting clock and to delay the generation of an output thereof by a delay time of an alternative mark bits-generating means; said alternative mark bits-generating means connected to another output of the retiming means to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits; CMI (II) code-generating means connected to an output of the space bits-generating and delaying means and an output of the alternative mark bits-generating means to convert a NRZ data received therefrom into a CMI (II) code, so that said mark bits and said space bits of a series of the NRZ data bits can be independently processed at the same time, in order to generate the CMI (II) code; and wherein said space bit-generating and delaying means comprise an OR-gate connected to said one output of the retiming means, and a delay element connected to the output of said OR-gate.
Claim 2
Dependent Claim
211 words
A NRZ to CMI (II) encoding circuit comprising: retiming means for retiming a series of NRZ data bits received thereto with a clock synchronized therewith; space bits-generating and delaying means connected to an output of said retiming means to compose space bits of a series of said received NRZ data bits and a NRZ data transmitting clock and to delay the generation of an output thereof by a delay time of an alternative mark bits-generating means; said alternative mark bits-generating means connected to another output of the retiming means to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits; CMI (II) code-generating means connected to an output of the space bits-generating and delaying means and an output of the alternative mark bits-generating means to convert a NRZ data received therefrom into a CMI (II) code, so that said mark bits and said space bits of a series of the NRZ data bits can be independently processed at the same time, in order to generate the CMI (II) code; and wherein said space bit-generating and delaying means comprise an OR-gate connected to said one output of the retiming means, and a delay element connected to the output of said OR-gate.
Claim 3
Dependent Claim
264 words
A NRZ to CMI (II) encoding circuit comprising: retiming means for retiming a series of NRZ data bits received thereto with a clock synchronized therewith; space bits-generating and delaying means connected to an output of said retiming means to compose space bits of a series of said received NRZ data bits and a NRZ data transmitting clock and to delay the generation of an output thereof by a delay of time of an alternative mark bits-generating means; said alternative mark bits-generating means connected to another output of the retiming means to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits; CMI (II) code-generating means connected to an output of the space bits-generating and delaying means and an output of the alternative mark bits-generating means to convert a NRZ data received therefrom into a CMI (II) code, so that said mark bits and said space bits of a series of the NRZ data bits can be independently processed at the same time, in order to generate the CMI (II) code; and wherein said alternative mark bits generating means comprise an OR-gate connected to the retiming means, and a D-type flip-flop having a data input, a clock input connected to the output of said OR-gate, and a negative output connected, in a feed-back fashion, to said data input so that said D-type flip-flop can be toggled to output a signal in the form of two-divided mark bits each time when a pulse indicative of the mark state is fed to said clock input thereof.
Claim 4
Dependent Claim
264 words
A NRZ to CMI (II) encoding circuit comprising: retiming means for retiming a series of NRZ data bits received thereto with a clock synchronized therewith; space bits-generating and delaying means connected to an output of said retiming means to compose space bits of a series of said received NRZ data bits and a NRZ data transmitting clock and to delay the generation of an output thereof by a delay of time of an alternative mark bits-generating means; said alternative mark bits-generating means connected to another output of the retiming means to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits; CMI (II) code-generating means connected to an output of the space bits-generating and delaying means and an output of the alternative mark bits-generating means to convert a NRZ data received therefrom into a CMI (II) code, so that said mark bits and said space bits of a series of the NRZ data bits can be independently processed at the same time, in order to generate the CMI (II) code; and wherein said alternative mark bits generating means comprise an OR-gate connected to the retiming means, and a D-type flip-flop having a data input, a clock input connected to the output of said OR-gate, and a negative output connected, in a feed-back fashion, to said data input so that said D-type flip-flop can be toggled to output a signal in the form of two-divided mark bits each time when a pulse indicative of the mark state is fed to said clock input thereof.
Claim 5
Dependent Claim
247 words
NRZ to CMI (II) encoding circuit comprising: retiming means for retiming a series of NRZ data bits received thereto with a clock synchronized therewith; space bits-generating and delaying means connected to an output of said retiming means to compose space bits of a series of said received NRZ data bits and a NRZ data transmitting clock and to delay the generation of an output thereof by a delay time of an alternative mark bits-generating means; said alternative mark bits-generating means connected to another output of the retiming means to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits; CMI (II) code-generating means connected to an output of the space bits-generating and delaying means and an output of the alternative mark bits-generating means to convert a NRZ data received therefrom into a CMI (II) code, so that said mark bits and said space bits of a series of the NRZ data bits can be independently processed for the same time, in order to generate the CMI (II) code; and wherein said CMI (II) code-generating means comprise an exclusive OR-gate in which mark bits are alternatively generated at the mark bit portions of a series of the NRZ data bits, and clock pulses are composed with a series of the NRZ data bits at the space bit portions of a series of the NRZ data bits, so that said OR-gate outputs a signal of the above-mentioned form.
Claim 6
Dependent Claim
247 words
NRZ to CMI (II) encoding circuit comprising: retiming means for retiming a series of NRZ data bits received thereto with a clock synchronized therewith; space bits-generating and delaying means connected to an output of said retiming means to compose space bits of a series of said received NRZ data bits and a NRZ data transmitting clock and to delay the generation of an output thereof by a delay time of an alternative mark bits-generating means; said alternative mark bits-generating means connected to another output of the retiming means to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits; CMI (II) code-generating means connected to an output of the space bits-generating and delaying means and an output of the alternative mark bits-generating means to convert a NRZ data received therefrom into a CMI (II) code, so that said mark bits and said space bits of a series of the NRZ data bits can be independently processed for the same time, in order to generate the CMI (II) code; and wherein said CMI (II) code-generating means comprise an exclusive OR-gate in which mark bits are alternatively generated at the mark bit portions of a series of the NRZ data bits, and clock pulses are composed with a series of the NRZ data bits at the space bit portions of a series of the NRZ data bits, so that said OR-gate outputs a signal of the above-mentioned form.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-21 | 1995-10-21 | 1996-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-21 | 1999-10-21 | 2000-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-21 | 2003-10-21 | 2004-04-21 | $7700.00 | Window Closed / Lapsed |