CMI Decoder

Claim 2

CMI decoder for the translation of CMI coded signals into binary signals with differential amplifiers connected to the input side of said decoder, comprising: a first; a second; and a third differential amplifier (T1, T2; T3, T4; T5, T6) wherein an input of a first stage (T1) of said first differential amplifier is connected to an input of a second stage (T4) of said second differential amplifier and to a first reference voltage source (Ur1); an input of a second stage (T2) of said first differential amplifier and of a first stage (T3) of said second differential amplifier being connected to each other and to an input terminal (E); said first differential amplifier forming with a first stage (T5) of said differential amplifier a first cascade circuit and said second differential amplifier forming with a second stage (T6) of said third differential amplifier a second cascade circuit; an input of said second stage of said third differential amplifier being connected to a second reference voltage source (Ur2) which is at a more negative potential relative to said first reference voltage source; an input of said first stage of said third differential amplifier being connected, via a time delay section τ with a delay corresponding to half a bit length, to said input (E) of said CMI decoder; and wherein outputs (A1 . . . A4) of said stages of said first and second differential amplifiers represent the outputs for binary signals which, upon being combined form a RZ signal.

Claim 3

CMI decoder according to claim 1, wherein said first stage of said first differential amplifier contains a first transistor (T1) whose collector terminal is connected to a first output terminal (A1) and, via a first resistor (R1), to a reference potential; said second stage of first differential amplifier contains a second transistor (T2) whose collector terminal is connected to a terminal for a third output (A3) and, via a third resistor (R3), to said reference potential; said first stage of said second differential amplifier contains a third transistor (T3) whose collector terminal is connected to a second output terminal (A2) and, via a second resistor (R2), to said reference potential; said second stage of said second differential amplifier contains a fourth transistor (T4) whose collector terminal is connected to a fourth output terminal (A4) and, via a fourth resistor (R4), to said reference potential; a first stage of said third differential amplifier contains a fifth transistor (T5) whose collector terminal is connected to the joined emitter terminals of said first and second transistors (T1, T2); a second stage of said third differential amplifier contains a sixth transistor (T6) whose collector terminal is connected to the joined emitter terminals of said third and fourth transistors (T3, T4); the base terminals of said first and fourth transistors (T1, T4) are connected to each other and to said first reference voltage source (Ur1); the base terminals of said second and third transistors (T2, T3) are connected to said input (E); and wherein the base terminal of said sixth transistor (T6) is connected to said second reference voltage source (Ur2).

Claim 4

CMI decoder according to claim 1, wherein when said time delay section (τ) is connected to said input (E) for generating binary signals, a third output (A3) and a fourth output (A4) are interconnected, for generating a joint output; and wherein a first output (1) is provided for connecting thereto a clock derivation circuit (TA).

Claim 5

CMI decoder according to claim 1, wherein when said time delay section (τ) is connected to said input (E') for handling an inverse CMI coded signal for generating binary signals, a first and second outputs (A1, A2) are interconnected, for generating a joint output of a binary RZ signal and wherein a fourth output (A4) is provided for connecting thereto a clock derivation circuit (TA).

Claim 6

CMI decoder according to claim 3, wherein said clock derivation circuit (TA) comprises a resonant circuit tuned to the clock frequency of said binary signals.

Claim 7

CMI decoder according to claim 3, further comprising a first and second D-flipflop and wherein the D-input of said first and second D-flipflop (Df1, Df2), are each separately connected to the binary signal outputs, the clock inputs of said flipflops being connected to each other and to the output of the clock derivation arrangement (TA) and that the inverting outputs (Q) of the two D-flipflops are connected to each other and to an output (BA) for timewise regenerated, binary signals.

Claim 8

CMI decoder according to claim 6, wherein the noninverting outputs (Q) of said two D-flipflops (Df1, Df2) are connected to two signal inputs of a code violation monitor (VM) whose clock input is connected to the output of said clock derivation circuit (TA) and whose output (MA) is connected to a monitoring device.

Claim 9

CMI decoder according to claim 7, wherein said CMI decoder is connected to the output (BA) for the timewise regenerated binary signals to produce amplitude- and time-generated CMI signals.