US4837782A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMI decoder
Assignee: NEC Corp
•
Filing: 1988-04-14
•
Granted: 1989-06-06
•
Expires: 2008-04-14
Abstract
Abstract In a digital communication system, a CMI (Coded Mark Inversion) decoder for extracting an optimum sampling timing from a CMI coded input signal so as to NRZ (Non-Return to Zero) format the input signal. A circuit for producing clock signals which are individually deviated in phase by +1/4 and -1/4 of a period relative to a reference clock signal that is extracted from the input signal is constituted by a logic circuit.
Inventors
- 👤 Eisaku Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:51
CPC Classifications
H; H03; H03M; H03M5/00; H03M5/02; H03M5/04; H03M5/06; H03M5/12; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908; H04L25/491; H04L25/4912; H04L7/00; H04L7/0054; H04L7/0066; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
195 words
A decoder for decoding a digitized signal into a CMI (Coded Mark Inversion) coded signal, comprising: a voltage controlled oscillator (VCO); 1/2 frequency dividing means for dividing an output of said VCO; first logic means supplied with an output of said VCO and an output of said 1/2 frequency dividing means for producing three clock signals, two of said three clock signals being individually deviated in phase by +1/4 and -1/4 of a period relative to a reference clock signal which is a remaining one of the three clock signals; first discriminating means for sampling a CMI coded input signal by the clock signal which is deviated by +1/4 of a period and outputted by said first logic means; second discriminating means for sampling the input signal by the reference clock signal, said VCO being controlled by an output of said second discriminating means; and third discriminating means for sampling the input signal by the clock signal which is deviated by -1/4 of a period; and second logic means supplied with an output of said first discriminating means and an output of said third discriminating means for producing a NRZ (Non-Return to Zero) format signal.
Claim 2
Dependent Claim
195 words
A decoder for decoding a digitized signal into a CMI (Coded Mark Inversion) coded signal, comprising: a voltage controlled oscillator (VCO); 1/2 frequency dividing means for dividing an output of said VCO; first logic means supplied with an output of said VCO and an output of said 1/2 frequency dividing means for producing three clock signals, two of said three clock signals being individually deviated in phase by +1/4 and -1/4 of a period relative to a reference clock signal which is a remaining one of the three clock signals; first discriminating means for sampling a CMI coded input signal by the clock signal which is deviated by +1/4 of a period and outputted by said first logic means; second discriminating means for sampling the input signal by the reference clock signal, said VCO being controlled by an output of said second discriminating means; and third discriminating means for sampling the input signal by the clock signal which is deviated by -1/4 of a period; and second logic means supplied with an output of said first discriminating means and an output of said third discriminating means for producing a NRZ (Non-Return to Zero) format signal.
Claim 3
Dependent Claim
18 words
A decoder as claimed in claim 1, wherein said 1/2 frequency dividing means comprises a toggle flip-flop circuit.
Claim 4
Dependent Claim
20 words
A decoder as claimed in claim 1, wherein said first logic means comprises an Exclusive-OR gate and an Exclusive-NOR gate.
Claim 5
Dependent Claim
27 words
A decoder as claimed in claim 1, wherein each of said first discriminating means, said second discriminating means and said third discriminating means comprises a flip-flop circuit.
Claim 6
Dependent Claim
16 words
A decoder as claimed in claim 1, wherein said second logic means comprises an Exclusive-NOR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-05 | 1992-12-05 | 1993-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-05 | 1996-12-05 | 1997-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-05 | 2000-12-05 | 2001-06-06 | $7700.00 | Window Closed / Lapsed |