EP0209306A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Phase-locked clock regeneration circuit for digital transmission systems
Assignee: NEC Corp
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Filing: 1986-07-07
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Granted: —
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Expires: 2006-07-07
Abstract
Abstract In a digital transmission system, a clock regeneration circuit includes a phase-locked loop (7) having a low-pass filter (71), a voltage-controlled oscillator (70) connected thereto, and a phase comparator (72) for supplying to the low-pass filter a signal representative of the phase difference between an incoming two-level data bit stream and the output of the voltage-controlled oscillator. The incoming data bit stream is converted (2) into a plurality of parallel data bit streams and fed to a multi-level quadrature amplitude modulator (4) in response to a clock signal derived from the output of the voltage-controlled oscillator and converted into an outgoing multi-level digital signal. An incoming CMI (coded mark inversion) coded binary signal is sampled by a flip-flop for in response to the output of the voltage-controlled oscillator to supply an output signal to the VCO through the low-pass filter.
Inventors
- 👤 Yasuharu C/O Nec Corporation Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 01:08
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/027; H04L7/033
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
125 words
A digital transmission system comprising: a phase-locked loop having a low-pass filter, a voltage-controlled oscillator connected thereto, and a phase comparator for supplying to said low-pass filter a signal representative of the phase difference between an incoming two-level data bit stream and an output of said voltage-controlled oscillator and generating a first, lower-frequency clock signal from said voltage-controlled oscillator; first means for converting said incoming data bit stream into a plurality of parallel data bit streams in response to said first click signal and deriving from the first clock signal a second, higher-frequency clock signal synchronized with said parallel data bit streams; and second means for converting said parallel data bit streams into an outgoing multi-level digital signal in response to said second clock signal.
Claim 2
Dependent Claim
125 words
A digital transmission system comprising: a phase-locked loop having a low-pass filter, a voltage-controlled oscillator connected thereto, and a phase comparator for supplying to said low-pass filter a signal representative of the phase difference between an incoming two-level data bit stream and an output of said voltage-controlled oscillator and generating a first, lower-frequency clock signal from said voltage-controlled oscillator; first means for converting said incoming data bit stream into a plurality of parallel data bit streams in response to said first click signal and deriving from the first clock signal a second, higher-frequency clock signal synchronized with said parallel data bit streams; and second means for converting said parallel data bit streams into an outgoing multi-level digital signal in response to said second clock signal.
Claim 3
Dependent Claim
45 words
A digital transmission system as claimed in claim 1, furthere comprising a tank circuit tuned to the frequency of the clock signal of said incoming data bit stream, said phase comparator comparing the outut of the tank circuit with the output of said voltage-controlled oscillator.
Claim 4
Dependent Claim
67 words
A digital transmission system as claimed in claim 1, wherein said incoming data bit stream comprises a CMI (coded mark inversion) coded binary signal, and wherein said phase comparator comprises a flip-flop having a first input terminal connected to be responsive to said CMI coded binary signal and a second input terminal responsive to the output of said votage-controlled oscillator for sampling said CMI coded binary signal.
Claim 5
Dependent Claim
150 words
A digital transmission system as claimed in claim 3, further comprising: delay means for deriving from the output of said voltage-controlled oscillator first and second output signals which are delayed and advanced with respect to the output of said voltage-controlled oscillator by a predetermined amount; second and third flip-flops each having a first input terminal connected to be responsive to said CMI coded binary signal and a second input terminal, the second input terminals of said second the third flip-flops being connected to be responsive to said first and second output signals of said delay means, respectively, for sampling said CMI coded binary signal at times respectively delayed and advanced with respect to the time at which the CMI coded binary signal is sampled by the first-mentioned flip-flop; and means for decoding the outputs of said second and third flip-flops and supplying a decoded output signal to said first means.
Claim 6
Dependent Claim
71 words
A clock regeneration circuit comprising: a flip-flop having a first input terminal responsive to a CMI (coded mark inversion) coded binary signal and a second input terminal; a low-pass filter connected to the output of said flip-flop; and a voltage-controlled oscillator for generating a clock pulse at a frequency variable as a function of an output signal from said low-pass filter and supplying said clock pulse to said second input terminal.
Claim 7
Dependent Claim
71 words
A clock regeneration circuit comprising: a flip-flop having a first input terminal responsive to a CMI (coded mark inversion) coded binary signal and a second input terminal; a low-pass filter connected to the output of said flip-flop; and a voltage-controlled oscillator for generating a clock pulse at a frequency variable as a function of an output signal from said low-pass filter and supplying said clock pulse to said second input terminal.
Claim 8
Dependent Claim
129 words
A clock regeneration circuit as claimed in claim 5, further comprising: delay means for deriving from the output of said voltage-controlled oscillator first and second output signals which are delayed and advanced with respect to the output of said voltage-controlled oscillator by a predetermined amount; and second and third flip-flops each having a first input terminal connected to be responsive to said CMI coded binary signal and a second input terminal, the second input terminals of said second and third flip-flops being connected to be responsive to said first and second output signals of said delay means, respectively, for sampling said CMI coded binary signal at times respectively delayed and advanced with respect to the time at which the CMI coded binary signal is sampled by the first-mentioned flip-flop.
References Cited (Backward Citations)
No citation records indexed.
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