Patent US5107148A successfully refreshed from Google Patents.
US5107148A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bidirectional buffer having tri-state buffers for circuit isolation
Assignee: NXP USA Inc
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Filing: 1991-04-12
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Granted: 1992-04-21
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Expires: 2011-04-12
Abstract
Abstract When testing one circuit block of a device, it is desired to have isolation from the other circuit blocks of the device so as to prevent possible failure of the other circuit blocks. A block isolation buffer includes a circuit for providing predetermined voltage levels at the inputs of the circuit blocks which are not being tested thereby assuring that an undesired input does not appear at the inputs of the non-tested circuit blocks.
Inventors
- 👤 Steven D. Millman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:38
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
178 words
A buffer circuit for providing isolation between circuit blocks within an integrated chip, comprising: a first tri-state inverter having an input and an output, said input of said first tri-state inverter being coupled to a first circuit block, said output of said first tri-state inverter being coupled to a circuit node; a second tri-state inverter having an input and an output, said input of said second tri-state inverter being coupled to said circuit node, said output of said second tri-state inverter being coupled to a second circuit block; a third tri-state inverter having an input and an output, said input of said third tri-state inverter being coupled to said circuit node, said output of said third tri-state inverter being coupled to a bi-directional terminal; a fourth tri-state inverter having an input and an output, said input of said fourth tri-state inverter being coupled to said bi-directional terminal, and said output of said fourth tri-state inverter being coupled to said circuit node; and means coupled to at least one of said circuit blocks for providing a predetermined voltage thereat.
Claim 2
Dependent Claim
178 words
A buffer circuit for providing isolation between circuit blocks within an integrated chip, comprising: a first tri-state inverter having an input and an output, said input of said first tri-state inverter being coupled to a first circuit block, said output of said first tri-state inverter being coupled to a circuit node; a second tri-state inverter having an input and an output, said input of said second tri-state inverter being coupled to said circuit node, said output of said second tri-state inverter being coupled to a second circuit block; a third tri-state inverter having an input and an output, said input of said third tri-state inverter being coupled to said circuit node, said output of said third tri-state inverter being coupled to a bi-directional terminal; a fourth tri-state inverter having an input and an output, said input of said fourth tri-state inverter being coupled to said bi-directional terminal, and said output of said fourth tri-state inverter being coupled to said circuit node; and means coupled to at least one of said circuit blocks for providing a predetermined voltage thereat.
Claim 3
Dependent Claim
51 words
The buffer circuit according to claim 1 wherein said means includes a transistor having first, second and control electrodes, said first electrode being coupled to said first circuit block, said control electrode being coupled to receive a test signal, and said second electrode being coupled to a first supply voltage terminal.
Claim 4
Dependent Claim
76 words
A buffer circuit for providing isolation between circuit blocks within an integrated chip, comprising: a first pair of tri-state inverters coupled between a first circuit block and a circuit node; a second pair of tri-state inverters coupled between a second circuit block and said circuit node; a third pair of tri-state inverters coupled between said circuit node and a bi-directional terminal; and means coupled to at least one circuit block for providing a predetermined voltage thereat.
Claim 5
Dependent Claim
76 words
A buffer circuit for providing isolation between circuit blocks within an integrated chip, comprising: a first pair of tri-state inverters coupled between a first circuit block and a circuit node; a second pair of tri-state inverters coupled between a second circuit block and said circuit node; a third pair of tri-state inverters coupled between said circuit node and a bi-directional terminal; and means coupled to at least one circuit block for providing a predetermined voltage thereat.
Claim 6
Dependent Claim
51 words
The buffer circuit according to claim 3 wherein said means includes a transistor having first, second and control electrodes, said first electrode being coupled to said first circuit block, said control electrode being coupled to receive a test signal, and said second electrode being coupled to a first supply voltage terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-21 | 1995-10-21 | 1996-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-21 | 1999-10-21 | 2000-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-21 | 2003-10-21 | 2004-04-21 | $7700.00 | Window Closed / Lapsed |