Abstract A counter includes an array of memory cells arranged in groups of memory cells, each group designating a counting decade, wherein each group of memory cells includes first and second word strings, each capable of storing a data word, and a fault flag, capable of indicating which word string contains the data word; sensing means coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell; logic means coupled to the memory cells and to the sensing means for selecting the first or second word string in response to a fault signal; wherein upon detection of a fault in a first word string, the data word is written into the second word string; and a central shifting unit coupled to the memory array for reading a data word stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.
Inventors
👤 Daniel H. Bennett
👤 Gary L. Dodd
👤 Kenelm G. D. Murray
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-29 14:41
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/40; H03K21/403
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
168 words
A counter comprising: an array of memory cells arranged in groups of memory cells, each group designating a counting decade, wherein each group of memory cells includes first and second work strings, each capable of storing a data word, and a fault flag, capable of indicating which work string contains a data word; sensing means coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell; logic means coupled to the fault flags and to the sensing means for selecting the first or second work string in response to a fault signal; wherein upon detection of a fault in a first work string, a data word is written into the second word string; and a central shifting unit coupled to the memory array for reading a data work stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.
Claim 2
Dependent Claim
168 words
A counter comprising: an array of memory cells arranged in groups of memory cells, each group designating a counting decade, wherein each group of memory cells includes first and second work strings, each capable of storing a data word, and a fault flag, capable of indicating which work string contains a data word; sensing means coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell; logic means coupled to the fault flags and to the sensing means for selecting the first or second work string in response to a fault signal; wherein upon detection of a fault in a first work string, a data word is written into the second word string; and a central shifting unit coupled to the memory array for reading a data work stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.
Claim 3
Dependent Claim
25 words
The counter of claim 1 wherein the sensing means includes a plurality of individual sensing circuits, each coupled to a particular group of memory cells.
Claim 4
Dependent Claim
25 words
The counter of claim 1 wherein the logic means includes a plurality of individual logic circuits, each coupled to a particular group of memory cells.