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US5105277A
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Process for canceling cell-to-cell performance variations in a sensor array
Assignee: Xerox Corp
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Filing: 1990-12-24
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Granted: 1992-04-14
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Expires: 2010-12-24
Abstract
Abstract A linear image sensor and process having a two stage transfer circuit in which split clock transistor actuating pulses are used to cancel cell-to-cell variations and neutralize undesired couplings of the rising edge of the charges into the transistors.
Inventors
- 👤 Frederick O. Hayes
- 👤 Paul A. Hosier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:35
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/67; H04N25/671; H04N25/672; H04N25/70; H04N25/701; H04N25/76; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/152
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
336 words
A process for canceling cell-to-cell variations in image sensor chips resulting from transistor threshold mismatches and clock edge couplings in which said sensor chips have an array of sensors; a common output bus to which the image charges accumulated by said sensors during an integration period are transferred to; a two stage transistor circuit coupling each of said sensors on a chip with said output bus having first transistor and second transistor disposed in series with one another; and an amplifier between said transistor circuit and said output bus for amplifying the image charges output by said sensors, comprising the steps of: a) providing a preset bias charge for application to a first node between said first and second transistors for use in setting the bias charge on said sensors; b) timing transfer of said bias charge to said sensors by said first transistor by applying a split clock actuating pulse to said first transistor so as to fill and spill said bias charge onto said sensors and prevent undesirable couplings of the rising edge of said bias charge into said first transistor while said first transistor is transferring said bias charge to said sensors; c) providing a preset reset charge for application to said first node; d) timing transfer of said reset charge by said second transistor to said first node by applying a second split clock actuating pulse to said second transistor so as to fill and spill said reset charge onto said first node and prevent undesirable couplings of the rising edge of said reset charge into said second transistor high level while said second transistor is setting said reset charge on said first node; e) continuing to provide said reset charge while inactivating said second transistor to apply said reset charge to a second node between said second transistor and said amplifier; and f) actuating said first and second transistors to transfer the image charges on said sensors through said first and second nodes to said amplifier for output to said bus.
Claim 2
Dependent Claim
336 words
A process for canceling cell-to-cell variations in image sensor chips resulting from transistor threshold mismatches and clock edge couplings in which said sensor chips have an array of sensors; a common output bus to which the image charges accumulated by said sensors during an integration period are transferred to; a two stage transistor circuit coupling each of said sensors on a chip with said output bus having first transistor and second transistor disposed in series with one another; and an amplifier between said transistor circuit and said output bus for amplifying the image charges output by said sensors, comprising the steps of: a) providing a preset bias charge for application to a first node between said first and second transistors for use in setting the bias charge on said sensors; b) timing transfer of said bias charge to said sensors by said first transistor by applying a split clock actuating pulse to said first transistor so as to fill and spill said bias charge onto said sensors and prevent undesirable couplings of the rising edge of said bias charge into said first transistor while said first transistor is transferring said bias charge to said sensors; c) providing a preset reset charge for application to said first node; d) timing transfer of said reset charge by said second transistor to said first node by applying a second split clock actuating pulse to said second transistor so as to fill and spill said reset charge onto said first node and prevent undesirable couplings of the rising edge of said reset charge into said second transistor high level while said second transistor is setting said reset charge on said first node; e) continuing to provide said reset charge while inactivating said second transistor to apply said reset charge to a second node between said second transistor and said amplifier; and f) actuating said first and second transistors to transfer the image charges on said sensors through said first and second nodes to said amplifier for output to said bus.
Claim 3
Dependent Claim
59 words
The process according to claim 1 in which said transistor circuit includes a third transistor adapted on actuation to input said bias charge, including the step of: timing input of said bias charge by said third transistor by applying a clock actuation pulse to said third transistor substantially simultaneously with said split clock actuation pulse to said first transistor.
Claim 4
Dependent Claim
59 words
The process according to claim 1 in which said transistor circuit includes a third transistor adapted on actuation to input said reset charge, including the step of: timing input of said reset charge by said third transistor by applying a clock actuation pulse to said third transistor substantially simultaneously with said split clock actuation pulse to said second transistor.
Claim 5
Dependent Claim
104 words
The process according to claim 1 in which said transistor circuit includes a third transistor adapted on actuation to input said bias charge and a fourth transistor adapted on actuation to input said reset charge, including the steps of: timing input of said bias charge by said third transistor by applying a clock actuation pulse to said third transistor substantially simultaneously with said split clock actuation pulse to said first transistor; and timing input of said reset charge by said fourth transistor by applying a clock actuation pulse to said fourth transistor substantially simultaneously with said split clock actuation pulse to said second transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-14 | 1995-10-14 | 1996-04-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-14 | 1999-10-14 | 2000-04-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-14 | 2003-10-14 | 2004-04-14 | $7700.00 | Window Closed / Lapsed |