Duty factor control circuit with variable output pulse width function

Claim 1

A duty factor control circuit for adjusting an input pulse such that a center of the adjusted input pulse coincides with an edge of a clock pulse, the control circuit comprising: first delay means including n serially connected first delay circuits, each of said first delay circuits delaying an input pulse thereto by a first non-zero predetermined period T, a center of an output of the nth first delay circuit coinciding with an edge of the clock pulse; first switching means for selecting an output of the (n-m)th first delay circuit; second delay means coupled to receive the selected output of said first switching means, and including n serially connected second delay circuits, each of said second delay circuits delaying an input thereto by a second predetermined period 2T which is twice the first predetermined period; second switching means for selecting an output of the mth second delay circuit; and logical means for outputting at least one of a logical AND and a logical OR between the selected outputs of said first and second switching means, wherein n and m are each an integer greater than 1, and wherein m is not greater than n.