Semiconductor memory

Claim 2

A semiconductor memory comprising a plurality of adjacent memory cells each including a transistor provided on a semiconductor substrate and a capacitor coupled to the transistor, each capacitor having an upper electrode, an insulating film and a lower electrode, one terminal of each of the transistors of the memory cells being connected to the lower electrode of a capacitor associated therewith, wherein the capacitors of the adjacent memory cells are opposed to each other, a part of the capacitors being superposed perpendicularly to the semiconductor substrate, said opposing capacitors being electrically isolated from one another and not sharing any common electrode between them.

Claim 3

A semiconductor memory according to claim 1 wherein the memory cell is of a stack type having a three-dimentional structure.

Claim 4

A semiconductor memory according to claim 2 wherein a plurality of node vane portions are provided for one node portion, the respective node vane portions being superposed on the opposite node vane portions of the adjacent capacitor perpendicularly to the semiconductor substrate.

Claim 5

A semiconductor memory according to claim 2 wherein the node vane portions are superposed on the opposite node vane portions of the adjacent capacitor through layer insulating films.

Claim 6

A semiconductor memory according to claim 1 wherein the lower electrode has a node portion and node vane portions which branch from the node portion and are extended in parallel with the semiconductor substrate toward respective adjacent capacitors; and wherein the upper electrode is opposed to the lower electrode via the insulating film.

Claim 7

A semiconductor memory according to claim 1 wherein the lower electrode has a node portion and node vane portions which branch from the node portion and are extended in parallel with the semiconductor substrate toward respective adjacent capacitors; wherein the upper electrode is opposed to the lower electrode via the insulating film; and wherein a bit line is located below the node vane portions.

Claim 8

A semiconductor memory according to claim 4 wherein the insulating film of the capacitor is formed at least on both upper and lower sides of the node vane portions.

Claim 9

A semiconductor memory comprising: a semiconductor substrate having a planar surface; a first memory cell including: a first transistor provided on said semiconductor substrate, said first transistor having a terminal, and a first elongated capacitor structure coupled to said first transistor terminal, said first capacitor structure comprising first and second elongated electrodes separated by an insulating film, said first elongated capacitor structure including a portion disposed substantially parallel to said substrate planar surface; a second memory cell adjacent to said first memory cell, said second memory cell including: a second transistor provided on said semiconductor substrate, said second transistor having a terminal, and a second elongated capacitor structure coupled to said second transistor terminal, said second capacitor structure having first and second electrodes separated by an insulating film, said second elongated capacitor structure having a portion which is disposed substantially parallel to said substrate planar surface; and an insulating layer disposed between said first and second elongated capacitor structures, said insulating layer electrically isolating said first and second capacitor structures from one another, wherein said first and second capacitor portions are substantially parallel to and oppose one another and are spaced apart from one another in a dimension perpendicular to the semiconductor substrate surface.

Claim 10

A semiconductor memory comprising: a semiconductor substrate having a planar surface; a first memory cell including: a first transistor provided on said semiconductor substrate, said first transistor having a terminal, and a first elongated capacitor structure coupled to said first transistor terminal, said first capacitor structure comprising first and second elongated electrodes separated by an insulating film, said first elongated capacitor structure including a portion disposed substantially parallel to said substrate planar surface; a second memory cell adjacent to said first memory cell, said second memory cell including: a second transistor provided on said semiconductor substrate, said second transistor having a terminal, and a second elongated capacitor structure coupled to said second transistor terminal, said second capacitor structure having first and second electrodes separated by an insulating film, said second elongated capacitor structure having a portion which is disposed substantially parallel to said substrate planar surface; and an insulating layer disposed between said first and second elongated capacitor structures, said insulating layer electrically isolating said first and second capacitor structures from one another, wherein said first and second capacitor portions are substantially parallel to and oppose one another and are spaced apart from one another in a dimension perpendicular to the semiconductor substrate surface.

Claim 11

A semiconductor memory according to claim 8, wherein the lower electrode has a node portion and node vane portions which branch from the node portion and are extended in parallel with the semiconductor substrate toward respective adjacent capacitors; and wherein the upper electrode is opposed to the lower electrode via the insulating film.

Claim 12

A semiconductor memory according to claim 8 wherein the lower electrode has a node portion and node vane portions which branch from the node portion and are extended in parallel with the semiconductor substrate toward respective adjacent capacitors; wherein the upper electrode is opposed to the lower electrode via the insulating film; and wherein a bit line is located below the node vane portions.