High speed low power dc offsetting circuit

Claim 2

A high speed, low power DC-offsetting circuit, comprising: an amplifier having an inverting input, a non-inverting input which is adapted to be connected to a high speed low DC voltage source and having an amplifier output; a current source which is connected to said inverting input and through a feedback resistor to said amplifier output; and capacitor means and resistor means, connected in series with each other, for connecting said non-inverting input to said amplifier output, said resistor means having one end connected to said amplifier output and having an opposite end connected to a DC-offsetting circuit output which is formed at the connection between said capacitor means and said resistor means.

Claim 3

The circuit of claim 1, wherein said capacitor means comprises a plurality of capacitors, in parallel with each other, for maintaining capacitive reactance over the frequency range of said source.

Claim 4

The circuit of claim 1, wherein said high speed low DC voltage source is a video amplifier which is connected to said non-inverting input through two resistors which are in series with each other; and wherein said capacitor means is connected to said non-inverting input by connecting it to the connection between said two resistors which are connected at a common point to said capacitor means.

Claim 5

The circuit of claim 1, wherein said amplifier output is connected to a ground reference through a capacitive load.

Claim 6

The circuit of claim 4, wherein said resistor means comprises two resistors in series with each other at a node which is connected to a said ground reference through capacitive means.

Claim 7

The circuit of claim 1, wherein said current source comprises bipolar digital to analog converter means whose output is a current which is a function of a digital input signal.

Claim 8

The circuit of claim 1, wherein said feedback resistor is adjustable.

Claim 9

The circuit of claim 1, wherein said current source comprises: voltage reference means for establishing a predetermined voltage reference and for connecting said non-inverting input to said inverting input through a resistor and to a voltage source through another resistor.

Claim 10

The circuit of claim 8, wherein said voltage reference comprises LM385 means.

Claim 11

The circuit of claim 1, wherein said amplifier comprises LF412 means.

Claim 12

A variable offset summer, comprising: a) an amplifier having an inverting input, a non-inverting input which is adapted to be connected to a high speed low DC voltage source and having an amplifier output, wherein said non-inverting input is connected to a video amplifier source through two resistors which are in series with each other; b) bipolar digital to analog converter means whose output is a current which is a function of a data input signal and which is connected to said inverting input and through a feedback resistor to said amplifier output; and c) capacitor means and resistor means, connected in series with each other at a circuit output node, for connecting said non-inverting input to said amplifier output, said resistor means being connected to said amplifier output.

Claim 13

A variable offset summer, comprising: a) an amplifier having an inverting input, a non-inverting input which is adapted to be connected to a high speed low DC voltage source and having an amplifier output, wherein said non-inverting input is connected to a video amplifier source through two resistors which are in series with each other; b) bipolar digital to analog converter means whose output is a current which is a function of a data input signal and which is connected to said inverting input and through a feedback resistor to said amplifier output; and c) capacitor means and resistor means, connected in series with each other at a circuit output node, for connecting said non-inverting input to said amplifier output, said resistor means being connected to said amplifier output.

Claim 14

The circuit of claim 11, wherein said capacitor means comprises at least two capacitors in parallel with each other for maintaining capacitive reactance over the frequency range of said source.

Claim 15

The circuit of claim 11, wherein said resistor means comprising two resistors which are connected in a series with each other and to ground through one capacitive means; and wherein said circuit output node is connected to ground through second capacitive means.

Claim 16

A fixed offset summer, comprising: a) amplifier means having an inverting input, a non-inverting input which is adapted to be connected to a high speed low DC voltage source and having an amplifier output which is connected to said inverting input through a resistance; b) voltage reference means for establishing a predetermined voltage reference and for connecting said non-inverting input to said inverting input through a resistor and to a voltage source through another resistor; and c) capacitor means and resistor means, connected in series with each other at a circuit output node, for connecting said non-inverting input to said amplifier output, said resistor means being connected to said amplifier output.

Claim 17

A fixed offset summer, comprising: a) amplifier means having an inverting input, a non-inverting input which is adapted to be connected to a high speed low DC voltage source and having an amplifier output which is connected to said inverting input through a resistance; b) voltage reference means for establishing a predetermined voltage reference and for connecting said non-inverting input to said inverting input through a resistor and to a voltage source through another resistor; and c) capacitor means and resistor means, connected in series with each other at a circuit output node, for connecting said non-inverting input to said amplifier output, said resistor means being connected to said amplifier output.

Claim 18

The circuit of claim 14, wherein said amplifier means comprises LF412 means.

Claim 19

The circuit of claim 14, wherein said voltage reference means comprises LM385 means.

Claim 20

The circuit of claim 14, wherein said resistance is adjustable to achieve a DC offset over a predetermined range.

Claim 21

The circuit of claim 14, wherein said capacitor comprises two capacitors in parallel with each other.

Claim 22

A circuit comprising: a) a high gain amplifier means having a non-inverting input, an inverting input which is connected to a DC coupled low frequency signal and having an amplifier output which is connected to said inverting input through a resistance; b) an input terminal for receiving a high speed DC coupled signal; and c) circuit means connected to said input terminal and to said non-inverting input, for passing said high speed DC coupled signal through one path including said high gain amplifier to a circuit output terminal and carrying through said one path DC and relatively low frequency signals up to a predetermined break frequency and for passing said high speed DC coupled signal through a second path to said circuit output terminal and carrying through said second path relatively high frequency signals from said break frequency to a predetermined upper frequency limit.

Claim 23

A circuit comprising: a) a high gain amplifier means having a non-inverting input, an inverting input which is connected to a DC coupled low frequency signal and having an amplifier output which is connected to said inverting input through a resistance; b) an input terminal for receiving a high speed DC coupled signal; and c) circuit means connected to said input terminal and to said non-inverting input, for passing said high speed DC coupled signal through one path including said high gain amplifier to a circuit output terminal and carrying through said one path DC and relatively low frequency signals up to a predetermined break frequency and for passing said high speed DC coupled signal through a second path to said circuit output terminal and carrying through said second path relatively high frequency signals from said break frequency to a predetermined upper frequency limit.

Claim 24

The circuit of claim 19, wherein said circuit means comprises: capacitor means connected at one end to said input terminal and at an opposite end to said circuit output terminal; and resistor means, connected to said opposite end of said capacitor means and to said circuit output terminal, for connecting said circuit output to said amplifier output.

Claim 25

A circuit for the level translation of a video signal, comprising: an amplifier having a non-inverting input which is adapted to receive a video signal, having an inverting input which is connected via a current source or sink means to ground and which is connected by a first resistor to a ground reference, and having an amplifier output which is connected to said inverting input by a second resistor; and the equivalent of a capacitor which is connected at one end to said non-inverting input and which is connected at its other end to a resistive circuit load and to one end of a third resistor which is connected at its other end to said amplifier output.

Claim 26

A circuit for the level translation of a video signal, comprising: an amplifier having a non-inverting input which is adapted to receive a video signal, having an inverting input which is connected via a current source or sink means to ground and which is connected by a first resistor to a ground reference, and having an amplifier output which is connected to said inverting input by a second resistor; and the equivalent of a capacitor which is connected at one end to said non-inverting input and which is connected at its other end to a resistive circuit load and to one end of a third resistor which is connected at its other end to said amplifier output.