Patent US5100829A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5100829A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for forming a semiconductor structure with closely coupled substrate temperature sense element

Assignee: Semiconductor Components Industries LLC
•
Filing: 1991-03-01
•
Granted: 1992-03-31
•
Expires: 2011-03-01
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.

Inventors

  • 👤 Gary V. Fay
  • 👤 Stephen P. Robb
  • 👤 Judith L. Sutor
  • 👤 Lewis E. Terry

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 19:26
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/611; H10D84/00; H10D84/101; H10D84/141; H10D84/143; H10D84/148; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 73 words
A process for forming a semiconductor structure combining active devices with a substrate temperature sensing element, comprising: providing a semiconductor substrate; forming, on the substrate, a dielectric having a first region of a first thickness of about 0.1 microns or less and a second region of a second, larger thickness; and forming on the first region a semiconductor PN junction electrically isolated from but thermally coupled to the substrate through the first region.
Claim 2
Dependent Claim 73 words
A process for forming a semiconductor structure combining active devices with a substrate temperature sensing element, comprising: providing a semiconductor substrate; forming, on the substrate, a dielectric having a first region of a first thickness of about 0.1 microns or less and a second region of a second, larger thickness; and forming on the first region a semiconductor PN junction electrically isolated from but thermally coupled to the substrate through the first region.
Claim 3
Dependent Claim 21 words
The process of claim 1 further comprising forming an over-voltage protection device electrically coupled between the PN junction and the substrate.
Claim 4
Dependent Claim 20 words
The process of claim 1 further comprising forming another PN junction coupled across the PN junction and in opposition thereto.
Claim 5
Dependent Claim 27 words
The process of claim 3 wherein the step of forming the PN junction comprises oppositely doping adjacent portions of a polycrystalline semiconductor layer over the first region.
Claim 6
Dependent Claim 30 words
The process of claim 2 wherein the step of forming the over-voltage protection device comprises forming at least two back-to-back PN junctions in a polycrystalline semiconductor on the second region.
Claim 7
Dependent Claim 32 words
The process of claim 1 wherein the step of forming a PN junction comprises forming a PN junction that is substantially at right angles to the dielectric surface in the first region.
Claim 8
Dependent Claim 19 words
The process of claim 1 further comprising coupling the PN junction to a gate electrode of an active device.
Claim 9
Dependent Claim 121 words
A process for forming a semiconductor structure employing active insulated gate field effect devices separated by an inactive field region, comprising: providing a substrate having a semiconductor surface; providing a dielectric layer on the semiconductor surface, wherein the dielectric layer has a first region of a first thickness of about 0.1 micrometers or less and is suitable for a gate dielectric for the active field effect devices and a second region of a second, larger, thickness suitable for the field region; providing a semiconductor PN junction located on the first region and thermally coupled to the semiconductor surface therethrough; and providing over-voltage protection means coupled to one side of the semiconductor PN junction for preventing electrical breakdown of the first region.
Claim 10
Dependent Claim 121 words
A process for forming a semiconductor structure employing active insulated gate field effect devices separated by an inactive field region, comprising: providing a substrate having a semiconductor surface; providing a dielectric layer on the semiconductor surface, wherein the dielectric layer has a first region of a first thickness of about 0.1 micrometers or less and is suitable for a gate dielectric for the active field effect devices and a second region of a second, larger, thickness suitable for the field region; providing a semiconductor PN junction located on the first region and thermally coupled to the semiconductor surface therethrough; and providing over-voltage protection means coupled to one side of the semiconductor PN junction for preventing electrical breakdown of the first region.
Claim 11
Dependent Claim 20 words
The process of claim 8 further comprising providing a further rectifying junction coupled across the PN junction in opposition thereto.
Claim 12
Dependent Claim 33 words
The process of claim 9 wherein the step of providing a further rectifying junction comprises providing a PN junction device having a breakdown voltage less than a rupture voltage of the first region.

References Cited (Backward Citations)

US4760434A Cited
JPS63299264A Cited
US4903106A Cited
US4896192A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-03-31 1995-09-30 1996-03-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-03-31 1999-09-30 2000-03-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-03-31 2003-09-30 2004-03-31 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag